drm/amd/powerplay: make gfx ds can be configure for sienna_cichlid

Make GFX deep sleep can be configure for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 75c31597a478f6cf4d0fcbc2571030394fe5da4b..49e157f2b39fdeed6be163351503208e978a4fbf 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -271,7 +271,6 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 
        *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
                                | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
-                               | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT)
                                | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
                                | FEATURE_MASK(FEATURE_THERMAL_BIT);
 
@@ -287,6 +286,9 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
        if (adev->pm.pp_feature & PP_ULV_MASK)
                *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 
+       if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
+               *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
+
        return 0;
 }