arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0

USB0 supports super-speed mode on the EVM. Enable that.
On the EVM, USB0 uses SERDES3 for super-speed lane.

Since USB0 is a type-C port, it needs to support lane swapping
for cable flip support. This is provided using SERDES lane
swap feature. Provide the Type-C cable orientation GPIO
to the SERDES Wrapper driver.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 861065a41c79574a83c5288df570a68a6af12a63..0c709af89f5bb1e3e2f21f3565e6f66a11a3efe4 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -109,6 +109,7 @@
        main_usbss0_pins_default: main_usbss0_pins_default {
                pinctrl-single,pins = <
                        J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+                       J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
                >;
        };
 
@@ -398,16 +399,43 @@
        status = "disabled";
 };
 
+&usb_serdes_mux {
+       idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
+};
+
+&serdes_ln_ctrl {
+       idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
+                     <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+                     <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
+                     <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
+                     <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz3 {
+       typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+};
+
+&serdes3 {
+       serdes3_usb_link: link@0 {
+               reg = <0>;
+               cdns,num-lanes = <2>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_USB3>;
+               resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+       };
+};
+
 &usbss0 {
        pinctrl-names = "default";
        pinctrl-0 = <&main_usbss0_pins_default>;
-       ti,usb2-only;
        ti,vbus-divider;
 };
 
 &usb0 {
        dr_mode = "otg";
-       maximum-speed = "high-speed";
+       maximum-speed = "super-speed";
+       phys = <&serdes3_usb_link>;
+       phy-names = "cdns3,usb3-phy";
 };
 
 &usbss1 {