ARM: dts: qcom: sdx65: Add support for A7 PLL clock

On SDX65 there is a separate A7 PLL which is used to provide high
frequency clock to the Cortex A7 CPU via a MUX.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-4-git-send-email-quic_rohiagar@quicinc.com

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 796641d30e06c2766d96c220bea8ad5565d754fa..6b3a502c0ce28f20f6cb08958e69a1644a5bbec0 100644 (file)
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -121,6 +121,14 @@
                              <0x17802000 0x1000>;
                };
 
+               a7pll: clock@17808000 {
+                       compatible = "qcom,sdx55-a7pll";
+                       reg = <0x17808000 0x1000>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>;
+                       clock-names = "bi_tcxo";
+                       #clock-cells = <0>;
+               };
+
                timer@17820000 {
                        #address-cells = <1>;
                        #size-cells = <1>;