static int port_forced;
static unsigned int synth_portlist[] = { 0x2a8, 0 };
-static struct var_t vars[] = {
- { CAPS_START, .u.s = {"[f130]" } },
- { CAPS_STOP, .u.s = {"[f90]" } },
- { RATE, .u.n = {"\04%c ", 8, 0, 10, 81, -8, NULL } },
- { PITCH, .u.n = {"[f%d]", 5, 0, 9, 40, 10, NULL } },
- { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
+
+enum default_vars_id {
+ CAPS_START_ID = 0, CAPS_STOP_ID,
+ RATE_ID, PITCH_ID,
+ DIRECT_ID, V_LAST_VAR_ID,
+ NB_ID
+};
+
+
+static struct var_t vars[NB_ID] = {
+ [CAPS_START_ID] = { CAPS_START, .u.s = {"[f130]" } },
+ [CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"[f90]" } },
+ [RATE_ID] = { RATE, .u.n = {"\04%c ", 8, 0, 10, 81, -8, NULL } },
+ [PITCH_ID] = { PITCH, .u.n = {"[f%d]", 5, 0, 9, 40, 10, NULL } },
+ [DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
V_LAST_VAR
};
module_param_hw_named(port, port_forced, int, ioport, 0444);
module_param_named(start, synth_keypc.startup, short, 0444);
+module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
+module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
+module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
MODULE_PARM_DESC(port, "Set the port for the synthesizer (override probing).");
MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
+MODULE_PARM_DESC(rate, "Set the rate variable on load.");
+MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
+MODULE_PARM_DESC(direct, "Set the direct variable on load.");
+
+
module_spk_synth(synth_keypc);