i2c: thunderx: Support for High speed mode

To support bus operations for high speed bus frequencies greater than
400KHZ following control bits need to be setup accordingly
 - hs_mode (bit 0) field in Mode register to switch controller
   between low-speed and high-speed frequency operating mode.
 - Setup clock divisors for desired TWSI bus frequency using
   FOSCL output frequency divisor (D):
   0 - sets the divisor to 10 for low speed mode
   1 - sets the divisor to 15 for high speed mode.
The TWSI bus output frequency, in master mode is based on:
                TCLK = 100MHz / (THP + 2)
                FOSCL = FSAMP / (M+1)×D = TCLK / (2 ^ N × (M + 1) × 15)
                FSAMP = TCLK / 2 ^ N
where,
        N is <2:0> and M is <6:3> of TWSI Clock Control Register
        D is 10 for low speed or 15 for HS_MODE

With high speed mode support, HLC mode usage is limited to
low speed frequency (<=400KHz) bus transfers in hardware.

Signed-off-by: Suneel Garapati <sgarapati@marvell.com>
Signed-off-by: Piyush Malgujar <pmalgujar@marvell.com>
Signed-off-by: Andi Shyti <andi.shyti@kernel.org>

diff --git a/drivers/i2c/busses/i2c-octeon-core.c b/drivers/i2c/busses/i2c-octeon-core.c
index 75efb375d8e49479267e214772d4df48352be358..86be597866f81c1bce54563047e14d099743f593 100644 (file)
--- a/drivers/i2c/busses/i2c-octeon-core.c
+++ b/drivers/i2c/busses/i2c-octeon-core.c
@@ -612,25 +612,27 @@ int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
        struct octeon_i2c *i2c = i2c_get_adapdata(adap);
        int i, ret = 0;
 
-       if (num == 1) {
-               if (msgs[0].len > 0 && msgs[0].len <= 8) {
-                       if (msgs[0].flags & I2C_M_RD)
-                               ret = octeon_i2c_hlc_read(i2c, msgs);
-                       else
-                               ret = octeon_i2c_hlc_write(i2c, msgs);
-                       goto out;
-               }
-       } else if (num == 2) {
-               if ((msgs[0].flags & I2C_M_RD) == 0 &&
-                   (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
-                   msgs[0].len > 0 && msgs[0].len <= 2 &&
-                   msgs[1].len > 0 && msgs[1].len <= 8 &&
-                   msgs[0].addr == msgs[1].addr) {
-                       if (msgs[1].flags & I2C_M_RD)
-                               ret = octeon_i2c_hlc_comp_read(i2c, msgs);
-                       else
-                               ret = octeon_i2c_hlc_comp_write(i2c, msgs);
-                       goto out;
+       if (IS_LS_FREQ(i2c->twsi_freq)) {
+               if (num == 1) {
+                       if (msgs[0].len > 0 && msgs[0].len <= 8) {
+                               if (msgs[0].flags & I2C_M_RD)
+                                       ret = octeon_i2c_hlc_read(i2c, msgs);
+                               else
+                                       ret = octeon_i2c_hlc_write(i2c, msgs);
+                               goto out;
+                       }
+               } else if (num == 2) {
+                       if ((msgs[0].flags & I2C_M_RD) == 0 &&
+                           (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&
+                           msgs[0].len > 0 && msgs[0].len <= 2 &&
+                           msgs[1].len > 0 && msgs[1].len <= 8 &&
+                           msgs[0].addr == msgs[1].addr) {
+                               if (msgs[1].flags & I2C_M_RD)
+                                       ret = octeon_i2c_hlc_comp_read(i2c, msgs);
+                               else
+                                       ret = octeon_i2c_hlc_comp_write(i2c, msgs);
+                               goto out;
+                       }
                }
        }
 
@@ -664,12 +666,12 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c)
 {
        int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
        bool is_plat_otx2;
-       unsigned int mdiv_min = 2;
        /*
         * Find divisors to produce target frequency, start with large delta
-        * to cover wider range of divisors, note thp = TCLK half period.
+        * to cover wider range of divisors, note thp = TCLK half period and
+        * ds is OSCL output frequency divisor.
         */
-       unsigned int thp = TWSI_MASTER_CLK_REG_DEF_VAL, mdiv = 2, ndiv = 0;
+       unsigned int thp, mdiv_min, mdiv = 2, ndiv = 0, ds = 10;
        unsigned int delta_hz = INITIAL_DELTA_HZ;
 
        is_plat_otx2 = octeon_i2c_is_otx2(to_pci_dev(i2c->dev));
@@ -677,6 +679,11 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c)
        if (is_plat_otx2) {
                thp = TWSI_MASTER_CLK_REG_OTX2_VAL;
                mdiv_min = 0;
+               if (!IS_LS_FREQ(i2c->twsi_freq))
+                       ds = 15;
+       } else {
+               thp = TWSI_MASTER_CLK_REG_DEF_VAL;
+               mdiv_min = 2;
        }
 
        for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
@@ -689,7 +696,7 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c)
                         * For given ndiv and mdiv values check the
                         * two closest thp values.
                         */
-                       tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
+                       tclk = i2c->twsi_freq * (mdiv_idx + 1) * ds;
                        tclk *= (1 << ndiv_idx);
                        if (is_plat_otx2)
                                thp_base = (i2c->sys_freq / tclk) - 2;
@@ -707,7 +714,9 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c)
                                        foscl = i2c->sys_freq /
                                                (2 * (thp_idx + 1));
                                foscl = foscl / (1 << ndiv_idx);
-                               foscl = foscl / (mdiv_idx + 1) / 10;
+                               foscl = foscl / (mdiv_idx + 1) / ds;
+                               if (foscl > i2c->twsi_freq)
+                                       continue;
                                diff = abs(foscl - i2c->twsi_freq);
                                /*
                                 * Diff holds difference between calculated frequency
@@ -725,6 +734,17 @@ void octeon_i2c_set_clock(struct octeon_i2c *i2c)
        }
        octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);
        octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
+       if (is_plat_otx2) {
+               u64 mode;
+
+               mode = __raw_readq(i2c->twsi_base + MODE(i2c));
+               /* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */
+               if (!IS_LS_FREQ(i2c->twsi_freq))
+                       mode |= TWSX_MODE_HS_MASK;
+               else
+                       mode &= ~TWSX_MODE_HS_MASK;
+               octeon_i2c_writeq_flush(mode, i2c->twsi_base + MODE(i2c));
+       }
 }
 
 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)

diff --git a/drivers/i2c/busses/i2c-octeon-core.h b/drivers/i2c/busses/i2c-octeon-core.h
index 69bd62940f99eb786877026380cd1d02a4eaadb9..94c4401a4a567c3bbe15ddb219bcb1a4fcb751bf 100644 (file)
--- a/drivers/i2c/busses/i2c-octeon-core.h
+++ b/drivers/i2c/busses/i2c-octeon-core.h
@@ -94,11 +94,18 @@ struct octeon_i2c_reg_offset {
        unsigned int sw_twsi;
        unsigned int twsi_int;
        unsigned int sw_twsi_ext;
+       unsigned int mode;
 };
 
 #define SW_TWSI(x)     (x->roff.sw_twsi)
 #define TWSI_INT(x)    (x->roff.twsi_int)
 #define SW_TWSI_EXT(x) (x->roff.sw_twsi_ext)
+#define MODE(x)                ((x)->roff.mode)
+
+/* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */
+#define TWSX_MODE_REFCLK_SRC   BIT(4)
+#define TWSX_MODE_HS_MODE      BIT(0)
+#define TWSX_MODE_HS_MASK      (TWSX_MODE_REFCLK_SRC | TWSX_MODE_HS_MODE)
 
 struct octeon_i2c {
        wait_queue_head_t queue;
@@ -213,6 +220,7 @@ static inline void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
        octeon_i2c_writeq_flush(data, i2c->twsi_base + TWSI_INT(i2c));
 }
 
+#define IS_LS_FREQ(twsi_freq)  ((twsi_freq) <= 400000)
 #define PCI_SUBSYS_DEVID_9XXX  0xB
 #define PCI_SUBSYS_MASK                GENMASK(15, 12)
 /**

diff --git a/drivers/i2c/busses/i2c-thunderx-pcidrv.c b/drivers/i2c/busses/i2c-thunderx-pcidrv.c
index 75569774003857dc984e8540ef8f4d1bb084cfb0..31f11b77ab663626967c86086a03213876bf4a07 100644 (file)
--- a/drivers/i2c/busses/i2c-thunderx-pcidrv.c
+++ b/drivers/i2c/busses/i2c-thunderx-pcidrv.c
@@ -166,6 +166,7 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev,
        i2c->roff.sw_twsi = 0x1000;
        i2c->roff.twsi_int = 0x1010;
        i2c->roff.sw_twsi_ext = 0x1018;
+       i2c->roff.mode = 0x1038;
 
        i2c->dev = dev;
        pci_set_drvdata(pdev, i2c);
@@ -210,7 +211,7 @@ static int thunder_i2c_probe_pci(struct pci_dev *pdev,
         * For OcteonTX2 chips, set reference frequency to 100MHz
         * as refclk_src in TWSI_MODE register defaults to 100MHz.
         */
-       if (octeon_i2c_is_otx2(pdev))
+       if (octeon_i2c_is_otx2(pdev) && IS_LS_FREQ(i2c->twsi_freq))
                i2c->sys_freq = OTX2_REF_FREQ_DEFAULT;
        octeon_i2c_set_clock(i2c);