arm64: dts: imx8m: Add ddr controller nodes

This is used by the imx-ddrc devfreq driver to implement dynamic
frequency scaling of DRAM.

Support for proactive scaling via interconnect will come later. The
high-performance bus masters which need that (display, vpu, gpu) are
mostly not yet enabled in upstream anyway.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index 28ab17a277bb92a193380db6dff3626c0719b169..cf044dde13e4fc9d9292194f52816a45c62dc553 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -77,6 +77,26 @@
        cpu-supply = <&buck2_reg>;
 };
 
+&ddrc {
+       operating-points-v2 = <&ddrc_opp_table>;
+
+       ddrc_opp_table: opp-table {
+               compatible = "operating-points-v2";
+
+               opp-25M {
+                       opp-hz = /bits/ 64 <25000000>;
+               };
+
+               opp-100M {
+                       opp-hz = /bits/ 64 <100000000>;
+               };
+
+               opp-750M {
+                       opp-hz = /bits/ 64 <750000000>;
+               };
+       };
+};
+
 &fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec1>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index da297b5e509dcad21ef161faddaa7708e36f0e28..20756440a420662787f447cb9718cb86e5d07eed 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -858,6 +858,16 @@
                        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               ddrc: memory-controller@3d400000 {
+                       compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
+                       reg = <0x3d400000 0x400000>;
+                       clock-names = "core", "pll", "alt", "apb";
+                       clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
+                                <&clk IMX8MM_DRAM_PLL>,
+                                <&clk IMX8MM_CLK_DRAM_ALT>,
+                                <&clk IMX8MM_CLK_DRAM_APB>;
+               };
+
                ddr-pmu@3d800000 {
                        compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
                        reg = <0x3d800000 0x400000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index 071949412cafd9fbb7faceefe983146c508e76e8..2497eebb57393b35799df2deaf1e2b1c07ca95bd 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -17,6 +17,26 @@
        cpu-supply = <&buck2_reg>;
 };
 
+&ddrc {
+       operating-points-v2 = <&ddrc_opp_table>;
+
+       ddrc_opp_table: opp-table {
+               compatible = "operating-points-v2";
+
+               opp-25M {
+                       opp-hz = /bits/ 64 <25000000>;
+               };
+
+               opp-100M {
+                       opp-hz = /bits/ 64 <100000000>;
+               };
+
+               opp-600M {
+                       opp-hz = /bits/ 64 <600000000>;
+               };
+       };
+};
+
 &i2c1 {
        pmic@4b {
                compatible = "rohm,bd71847";

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index aa95f76de5ef0e3e4a2daedb21276ef7e562a23c..dc8cd5193e4ae8d9cc87ed1a5517adc3ed7edabe 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -759,6 +759,16 @@
                        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               ddrc: memory-controller@3d400000 {
+                       compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
+                       reg = <0x3d400000 0x400000>;
+                       clock-names = "core", "pll", "alt", "apb";
+                       clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
+                                <&clk IMX8MN_DRAM_PLL>,
+                                <&clk IMX8MN_CLK_DRAM_ALT>,
+                                <&clk IMX8MN_CLK_DRAM_APB>;
+               };
+
                ddr-pmu@3d800000 {
                        compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
                        reg = <0x3d800000 0x400000>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index c36685916683ef40581749193240fa197334912f..94066d49d6ed5c7917bd0b77212916aba41dd4ad 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -105,6 +105,33 @@
        cpu-supply = <&buck2_reg>;
 };
 
+&ddrc {
+       operating-points-v2 = <&ddrc_opp_table>;
+
+       ddrc_opp_table: opp-table {
+               compatible = "operating-points-v2";
+
+               opp-25M {
+                       opp-hz = /bits/ 64 <25000000>;
+               };
+
+               opp-100M {
+                       opp-hz = /bits/ 64 <100000000>;
+               };
+
+               /*
+                * On imx8mq B0 PLL can't be bypassed so low bus is 166M
+                */
+               opp-166M {
+                       opp-hz = /bits/ 64 <166935483>;
+               };
+
+               opp-800M {
+                       opp-hz = /bits/ 64 <800000000>;
+               };
+       };
+};
+
 &fec1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec1>;

diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 7f9319452b58533be57e95eecee44eeb3895a193..d1fcf9887f8b88419e965d6a6f13c35d28f3fbb7 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1113,6 +1113,16 @@
                        interrupt-parent = <&gic>;
                };
 
+               ddrc: memory-controller@3d400000 {
+                       compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
+                       reg = <0x3d400000 0x400000>;
+                       clock-names = "core", "pll", "alt", "apb";
+                       clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
+                                <&clk IMX8MQ_DRAM_PLL_OUT>,
+                                <&clk IMX8MQ_CLK_DRAM_ALT>,
+                                <&clk IMX8MQ_CLK_DRAM_APB>;
+               };
+
                ddr-pmu@3d800000 {
                        compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
                        reg = <0x3d800000 0x400000>;