riscv: remove riscv_isa_ext_keys[] array and related usage

All users have switched to riscv_has_extension_*, remove unused
definitions, vars and related setting code.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20230128172856.3814-14-jszhang@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 411ef0fb5c4b68dbeac88568b98590eac5148e91..7936ae6f7bdfbf3dda4587df4fcfa8ccb5d1e83b 100644 (file)
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -61,20 +61,6 @@ enum {
 
 extern unsigned long elf_hwcap;
 
-
-/*
- * This enum represents the logical ID for each RISC-V ISA extension static
- * keys. We can use static key to optimize code path if some ISA extensions
- * are available.
- * Entries are sorted alphabetically.
- */
-enum riscv_isa_ext_key {
-       RISCV_ISA_EXT_KEY_FPU,          /* For 'F' and 'D' */
-       RISCV_ISA_EXT_KEY_SVINVAL,
-       RISCV_ISA_EXT_KEY_ZIHINTPAUSE,
-       RISCV_ISA_EXT_KEY_MAX,
-};
-
 struct riscv_isa_ext_data {
        /* Name of the extension displayed to userspace via /proc/cpuinfo */
        char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
@@ -82,24 +68,6 @@ struct riscv_isa_ext_data {
        unsigned int isa_ext_id;
 };
 
-extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX];
-
-static __always_inline int riscv_isa_ext2key(int num)
-{
-       switch (num) {
-       case RISCV_ISA_EXT_f:
-               return RISCV_ISA_EXT_KEY_FPU;
-       case RISCV_ISA_EXT_d:
-               return RISCV_ISA_EXT_KEY_FPU;
-       case RISCV_ISA_EXT_SVINVAL:
-               return RISCV_ISA_EXT_KEY_SVINVAL;
-       case RISCV_ISA_EXT_ZIHINTPAUSE:
-               return RISCV_ISA_EXT_KEY_ZIHINTPAUSE;
-       default:
-               return -EINVAL;
-       }
-}
-
 static __always_inline bool
 riscv_has_extension_likely(const unsigned long ext)
 {

diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 18ea518f9e68d5638dbfb1c80023b92c340ffc0a..a4f737bc75304c573b2f5c9927b4a1749e3e7d78 100644 (file)
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -29,9 +29,6 @@ unsigned long elf_hwcap __read_mostly;
 /* Host ISA bitmap */
 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
 
-DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
-EXPORT_SYMBOL(riscv_isa_ext_keys);
-
 /**
  * riscv_isa_extension_base() - Get base extension word
  *
@@ -267,12 +264,6 @@ void __init riscv_fill_hwcap(void)
                if (elf_hwcap & BIT_MASK(i))
                        print_str[j++] = (char)('a' + i);
        pr_info("riscv: ELF capabilities %s\n", print_str);
-
-       for_each_set_bit(i, riscv_isa, RISCV_ISA_EXT_MAX) {
-               j = riscv_isa_ext2key(i);
-               if (j >= 0)
-                       static_branch_enable(&riscv_isa_ext_keys[j]);
-       }
 }
 
 #ifdef CONFIG_RISCV_ALTERNATIVE