drm: rcar-du: Add r8a779g0 support

Add support for DU on r8a779g0, which is identical to DU on r8a779a0.

Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index fb39d60306bb5248ddf805d2f43102fc86eb5f5b..c7c5217cfc1a033a546b33e0dffdb59397048736 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -524,6 +524,27 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
        .dsi_clk_mask =  BIT(1) | BIT(0),
 };
 
+static const struct rcar_du_device_info rcar_du_r8a779g0_info = {
+       .gen = 4,
+       .features = RCAR_DU_FEATURE_CRTC_IRQ
+                 | RCAR_DU_FEATURE_VSP1_SOURCE
+                 | RCAR_DU_FEATURE_NO_BLENDING,
+       .channels_mask = BIT(1) | BIT(0),
+       .routes = {
+               /* R8A779G0 has two MIPI DSI outputs. */
+               [RCAR_DU_OUTPUT_DSI0] = {
+                       .possible_crtcs = BIT(0),
+                       .port = 0,
+               },
+               [RCAR_DU_OUTPUT_DSI1] = {
+                       .possible_crtcs = BIT(1),
+                       .port = 1,
+               },
+       },
+       .num_rpf = 5,
+       .dsi_clk_mask =  BIT(1) | BIT(0),
+};
+
 static const struct of_device_id rcar_du_of_table[] = {
        { .compatible = "renesas,du-r8a7742", .data = &rcar_du_r8a7790_info },
        { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
@@ -549,6 +570,7 @@ static const struct of_device_id rcar_du_of_table[] = {
        { .compatible = "renesas,du-r8a77990", .data = &rcar_du_r8a7799x_info },
        { .compatible = "renesas,du-r8a77995", .data = &rcar_du_r8a7799x_info },
        { .compatible = "renesas,du-r8a779a0", .data = &rcar_du_r8a779a0_info },
+       { .compatible = "renesas,du-r8a779g0", .data = &rcar_du_r8a779g0_info },
        { }
 };
 

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c
index 1fe8581577edba3bdf8d40a620c641a558b3400c..6da01760ede51bdf2d17fbfb3f1c98cd90285001 100644 (file)
--- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
@@ -107,7 +107,7 @@ static void rcar_du_group_setup_didsr(struct rcar_du_group *rgrp)
                 */
                rcrtc = rcdu->crtcs;
                num_crtcs = rcdu->num_crtcs;
-       } else if (rcdu->info->gen == 3 && rgrp->num_crtcs > 1) {
+       } else if (rcdu->info->gen >= 3 && rgrp->num_crtcs > 1) {
                /*
                 * On Gen3 dot clocks are setup through per-group registers,
                 * only available when the group has two channels.