<&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
<&pcc4 IMX8ULP_CLK_USDHC0>;
clock-names = "ipg", "ahb", "per";
+ power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
<&pcc4 IMX8ULP_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
+ power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
<&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
<&pcc4 IMX8ULP_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per";
+ power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;