drm/amdgpu: enable VCN RAS poison for VCN v4.0

Configure related registers.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 66b3f42764df005c9ce37d2a7d3bce4fa46d5f4a..1e2b22299975ffba902ec00a9ed8d6a84d2b6494 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -862,6 +862,28 @@ static void vcn_v4_0_enable_clock_gating(struct amdgpu_device *adev, int inst)
        return;
 }
 
+static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx,
+                               bool indirect)
+{
+       uint32_t tmp;
+
+       if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__VCN))
+               return;
+
+       tmp = VCN_RAS_CNTL__VCPU_VCODEC_REARM_MASK |
+             VCN_RAS_CNTL__VCPU_VCODEC_IH_EN_MASK |
+             VCN_RAS_CNTL__VCPU_VCODEC_PMI_EN_MASK |
+             VCN_RAS_CNTL__VCPU_VCODEC_STALL_EN_MASK;
+       WREG32_SOC15_DPG_MODE(inst_idx,
+                             SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL),
+                             tmp, 0, indirect);
+
+       tmp = UVD_SYS_INT_EN__RASCNTL_VCPU_VCODEC_EN_MASK;
+       WREG32_SOC15_DPG_MODE(inst_idx,
+                             SOC15_DPG_MODE_OFFSET(VCN, 0, regUVD_SYS_INT_EN),
+                             tmp, 0, indirect);
+}
+
 /**
  * vcn_v4_0_start_dpg_mode - VCN start with dpg mode
  *
@@ -950,6 +972,8 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
        WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
                VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);
 
+       vcn_v4_0_enable_ras(adev, inst_idx, indirect);
+
        /* enable master interrupt */
        WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
                VCN, inst_idx, regUVD_MASTINT_EN),