riscv: lib: uaccess: fix CSR_STATUS SR_SUM bit

[ Upstream commit c08b4848f596fd95543197463b5162bd7bab2442 ]

Since commit 5d8544e2d007 ("RISC-V: Generic library routines and assembly")
and commit ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code"),
if __clear_user and __copy_user return from an fixup branch,
CSR_STATUS SR_SUM bit will be set, it is a vulnerability, so that
S-mode memory accesses to pages that are accessible by U-mode will success.
Disable S-mode access to U-mode memory should clear SR_SUM bit.

Fixes: 5d8544e2d007 ("RISC-V: Generic library routines and assembly")
Fixes: ebcbd75e3962 ("riscv: Fix the bug in memory access fixup code")
Signed-off-by: Chen Lifu <chenlifu@huawei.com>
Reviewed-by: Ben Dooks <ben.dooks@codethink.co.uk>
Link: https://lore.kernel.org/r/20220615014714.1650349-1-chenlifu@huawei.com
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S
index ac34f0026adcd681653bc0150889f20ee8bb606d..2c7c1c5026af394faafd3d0a02f2eb07f742ca65 100644 (file)
--- a/arch/riscv/lib/uaccess.S
+++ b/arch/riscv/lib/uaccess.S
@@ -177,7 +177,7 @@ ENTRY(__asm_copy_from_user)
        /* Exception fixup code */
 10:
        /* Disable access to user memory */
-       csrs CSR_STATUS, t6
+       csrc CSR_STATUS, t6
        mv a0, t5
        ret
 ENDPROC(__asm_copy_to_user)
@@ -229,7 +229,7 @@ ENTRY(__clear_user)
        /* Exception fixup code */
 11:
        /* Disable access to user memory */
-       csrs CSR_STATUS, t6
+       csrc CSR_STATUS, t6
        mv a0, a1
        ret
 ENDPROC(__clear_user)