drm/amd/display: Only use ODM2:1 policy for high pixel rate displays

We only gain a benefit of using the ODM2:1 dynamic policy if it allow us
to decrease DISPCLK to use the VMIN freq.  If the display config can
already achieve VMIN DISPCLK freq without ODM2:1, don't apply the
policy.

Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
index b6bf4c74d6bf65839e2383b48913ece1211d9d6b..05de97ea855f1bc590f2e2a55634cb07335f6190 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
@@ -1872,6 +1872,7 @@ int dcn32_populate_dml_pipes_from_context(
                                context->stream_status[0].plane_count <= 1 &&
                                !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) &&
                                is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) &&
+                               pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ &&
                                dc->debug.enable_single_display_2to1_odm_policy) {
                        pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
                }

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
index 40e9211eec1e47229157a897b9e7b4d5e5c8e212..55945cca2260dcf0886a54970183c50d65fd813f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -37,6 +37,7 @@
 #define DCN3_2_MBLK_WIDTH 128
 #define DCN3_2_MBLK_HEIGHT_4BPE 128
 #define DCN3_2_MBLK_HEIGHT_8BPE 64
+#define DCN3_2_VMIN_DISPCLK_HZ 717000000
 
 #define TO_DCN32_RES_POOL(pool)\
        container_of(pool, struct dcn32_resource_pool, base)