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MIPS: dts: mscc: describe the PTP register range
author
Antoine Tenart
<antoine.tenart@bootlin.com>
Wed, 24 Jul 2019 08:17:09 +0000
(10:17 +0200)
committer
Paul Burton
<paul.burton@mips.com>
Sat, 24 Aug 2019 14:17:33 +0000
(15:17 +0100)
This patch adds one register range within the mscc,vsc7514-switch node,
to describe the PTP registers.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: davem@davemloft.net
Cc: richardcochran@gmail.com
Cc: alexandre.belloni@bootlin.com
Cc: UNGLinuxDriver@microchip.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: netdev@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
Cc: allan.nielsen@microchip.com
arch/mips/boot/dts/mscc/ocelot.dtsi
patch
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diff --git
a/arch/mips/boot/dts/mscc/ocelot.dtsi
b/arch/mips/boot/dts/mscc/ocelot.dtsi
index 33ae74aaa1bb2f3fcb62869821bd5596bbdbf973..1e55a778def5a215dc005954ed9f6edace9022eb 100644
(file)
--- a/
arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/
arch/mips/boot/dts/mscc/ocelot.dtsi
@@
-120,6
+120,7
@@
reg = <0x1010000 0x10000>,
<0x1030000 0x10000>,
<0x1080000 0x100>,
+ <0x10e0000 0x10000>,
<0x11e0000 0x100>,
<0x11f0000 0x100>,
<0x1200000 0x100>,
@@
-134,7
+135,7
@@
<0x1800000 0x80000>,
<0x1880000 0x10000>,
<0x1060000 0x10000>;
- reg-names = "sys", "rew", "qs", "port0", "port1",
+ reg-names = "sys", "rew", "qs", "p
tp", "p
ort0", "port1",
"port2", "port3", "port4", "port5", "port6",
"port7", "port8", "port9", "port10", "qsys",
"ana", "s2";