msgs[dev->msg_write_idx].addr | ic_tar);
/* Enforce disabled interrupts (due to HW issues) */
- regmap_write(dev->map, DW_IC_INTR_MASK, 0);
+ __i2c_dw_write_intr_mask(dev, 0);
/* Enable the adapter */
__i2c_dw_enable(dev);
if (dev->msg_err)
intr_mask = 0;
- regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask);
+ __i2c_dw_write_intr_mask(dev, intr_mask);
}
static u8
{
struct i2c_msg *msgs = dev->msgs;
u32 flags = msgs[dev->msg_read_idx].flags;
+ unsigned int intr_mask;
/*
* Adjust the buffer length and mask the flag
* Received buffer length, re-enable TX_EMPTY interrupt
* to resume the SMBUS transaction.
*/
- regmap_update_bits(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_TX_EMPTY,
- DW_IC_INTR_TX_EMPTY);
+ __i2c_dw_read_intr_mask(dev, &intr_mask);
+ intr_mask |= DW_IC_INTR_TX_EMPTY;
+ __i2c_dw_write_intr_mask(dev, intr_mask);
return len;
}
* interrupt really came from this HW (E.g. firmware has left
* the HW active).
*/
- regmap_write(dev->map, DW_IC_INTR_MASK, 0);
+ __i2c_dw_write_intr_mask(dev, 0);
return IRQ_HANDLED;
}
* Anytime TX_ABRT is set, the contents of the tx/rx
* buffers are flushed. Make sure to skip them.
*/
- regmap_write(dev->map, DW_IC_INTR_MASK, 0);
+ __i2c_dw_write_intr_mask(dev, 0);
goto tx_aborted;
}
complete(&dev->cmd_complete);
else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
/* Workaround to trigger pending interrupt */
- regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
- regmap_write(dev->map, DW_IC_INTR_MASK, 0);
- regmap_write(dev->map, DW_IC_INTR_MASK, stat);
+ __i2c_dw_read_intr_mask(dev, &stat);
+ __i2c_dw_write_intr_mask(dev, 0);
+ __i2c_dw_write_intr_mask(dev, stat);
}
return IRQ_HANDLED;
if (ret)
return ret;
- regmap_write(dev->map, DW_IC_INTR_MASK, 0);
+ __i2c_dw_write_intr_mask(dev, 0);
i2c_dw_release_lock(dev);
if (!(dev->flags & ACCESS_POLLING)) {