pinctrl: renesas: rzg2l: Improve code for readability

As the RZ/G2L pinctrl driver is extensively utilized by numerous SoCs and
has experienced substantial growth, enhance code readability by
incorporating FIELD_PREP_CONST/FIELD_GET macros wherever necessary.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240129135556.63466-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 01ef6921cb35c79f5136e915a499dc9d7c6cd3fb..90fb67bc473f86e5fae993e55c729311fd2d85be 100644 (file)
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -5,6 +5,7 @@
  * Copyright (C) 2021 Renesas Electronics Corporation.
  */
 
+#include <linux/bitfield.h>
 #include <linux/bitops.h>
 #include <linux/clk.h>
 #include <linux/gpio/driver.h>
@@ -38,8 +39,6 @@
  */
 #define MUX_PIN_ID_MASK                GENMASK(15, 0)
 #define MUX_FUNC_MASK          GENMASK(31, 16)
-#define MUX_FUNC_OFFS          16
-#define MUX_FUNC(pinconf)      (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
 
 /* PIN capabilities */
 #define PIN_CFG_IOLH_A                 BIT(0)
@@ -81,8 +80,12 @@
  * n indicates number of pins in the port, a is the register index
  * and f is pin configuration capabilities supported.
  */
-#define RZG2L_GPIO_PORT_PACK(n, a, f)  (((n) << 28) | ((a) << 20) | (f))
-#define RZG2L_GPIO_PORT_GET_PINCNT(x)  (((x) & GENMASK(30, 28)) >> 28)
+#define PIN_CFG_PIN_CNT_MASK           GENMASK(30, 28)
+#define PIN_CFG_PIN_REG_MASK           GENMASK(27, 20)
+#define PIN_CFG_MASK                   GENMASK(19, 0)
+#define RZG2L_GPIO_PORT_PACK(n, a, f)  (FIELD_PREP_CONST(PIN_CFG_PIN_CNT_MASK, (n)) | \
+                                        FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \
+                                        FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
 
 /*
  * BIT(31) indicates dedicated pin, p is the register index while
@@ -90,14 +93,17 @@
  * (b * 8) and f is the pin configuration capabilities supported.
  */
 #define RZG2L_SINGLE_PIN               BIT(31)
+#define RZG2L_SINGLE_PIN_INDEX_MASK    GENMASK(30, 24)
+#define RZG2L_SINGLE_PIN_BITS_MASK     GENMASK(22, 20)
+
 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \
-                                        ((p) << 24) | ((b) << 20) | (f))
-#define RZG2L_SINGLE_PIN_GET_BIT(x)    (((x) & GENMASK(22, 20)) >> 20)
+                                        FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \
+                                        FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \
+                                        FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
 
-#define RZG2L_PIN_CFG_TO_CAPS(cfg)             ((cfg) & GENMASK(19, 0))
 #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg)      ((cfg) & RZG2L_SINGLE_PIN ? \
-                                               (((cfg) & GENMASK(30, 24)) >> 24) : \
-                                               (((cfg) & GENMASK(26, 20)) >> 20))
+                                                FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \
+                                                FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg)))
 
 #define P(off)                 (0x0000 + (off))
 #define PM(off)                        (0x0100 + (off) * 2)
@@ -432,8 +438,8 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev,
                ret = of_property_read_u32_index(np, "pinmux", i, &value);
                if (ret)
                        goto done;
-               pins[i] = value & MUX_PIN_ID_MASK;
-               psel_val[i] = MUX_FUNC(value);
+               pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value);
+               psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value);
        }
 
        if (parent) {
@@ -560,7 +566,7 @@ done:
 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl,
                                   u32 cfg, u32 port, u8 bit)
 {
-       u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg);
+       u8 pincount = FIELD_GET(PIN_CFG_PIN_CNT_MASK, cfg);
        u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg);
        u32 data;
 
@@ -866,9 +872,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
                return -EINVAL;
 
        off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
-       cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data);
+       cfg = FIELD_GET(PIN_CFG_MASK, *pin_data);
        if (*pin_data & RZG2L_SINGLE_PIN) {
-               bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
+               bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);
        } else {
                bit = RZG2L_PIN_ID_TO_PIN(_pin);
 
@@ -970,9 +976,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
                return -EINVAL;
 
        off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
-       cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data);
+       cfg = FIELD_GET(PIN_CFG_MASK, *pin_data);
        if (*pin_data & RZG2L_SINGLE_PIN) {
-               bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data);
+               bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data);
        } else {
                bit = RZG2L_PIN_ID_TO_PIN(_pin);
 
@@ -1608,12 +1614,12 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_
        bit = virq % 8;
 
        if (port >= data->n_ports ||
-           bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port]))
+           bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[port]))
                return -EINVAL;
 
        gpioint = bit;
        for (i = 0; i < port; i++)
-               gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]);
+               gpioint += FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[i]);
 
        return gpioint;
 }
@@ -1788,7 +1794,7 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc,
                bit = offset % 8;
 
                if (port >= pctrl->data->n_ports ||
-                   bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port]))
+                   bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, pctrl->data->port_pin_configs[port]))
                        clear_bit(offset, valid_mask);
        }
 }