drm/msm/dsi: Use "ref" fw clock instead of global name for VCO parent
authorMarijn Suijten <marijn.suijten@somainline.org>
Sat, 11 Sep 2021 13:19:20 +0000 (15:19 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 8 Apr 2022 12:23:33 +0000 (14:23 +0200)
[ Upstream commit 3a3ee71bd8e14c5e852c71f317eebfda8f88dff0 ]

All DSI PHY/PLL drivers were referencing their VCO parent clock by a
global name, most of which don't exist or have been renamed.  These
clock drivers seem to function fine without that except the 14nm driver
for sdm6xx [1].

At the same time all DTs provide a "ref" clock as per the requirements
of dsi-phy-common.yaml, but the clock is never used.  This patchset puts
that clock to use without relying on a global clock name, so that all
dependencies are explicitly defined in DT (the firmware) in the end.

Note that this patch intentionally breaks older firmware (DT) that
relies on the clock to be found globally instead.  The only affected
platform is msm8974 [2] for whose dsi_phy_28nm a .name="xo" fallback is
left in place to accommodate a more graceful transition period.  All
other platforms had the "ref" clock added to their phy node since its
inception, or in a followup patch some time after.  These patches
wrongly assumed that the "ref" clock was actively used and have hence
been listed as "Fixes:" below.
Furthermore apq8064 was providing the wrong 19.2MHz cxo instead of
27MHz pxo clock, which has been addressed in [3].

It is expected that both [2] and [3] are applied to the tree well in
advance of this patch such that any actual breakage is extremely
unlikely, but might still occur if kernel upgrades are performed without
the DT to match.  After some time the fallback for msm8974 can be
removed again as well.

[1]: https://lore.kernel.org/linux-arm-msm/386db1a6-a1cd-3c7d-a88e-dc83f8a1be96@somainline.org/
[2]: https://lore.kernel.org/linux-arm-msm/20210830175739.143401-1-marijn.suijten@somainline.org/
[3]: https://lore.kernel.org/linux-arm-msm/20210829203027.276143-2-marijn.suijten@somainline.org/

Fixes: 79e51645a1dd ("arm64: dts: qcom: msm8916: Set 'xo_board' as ref clock of the DSI PHY")
Fixes: 6969d1d9c615 ("ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY")
Fixes: 0c0e72705a33 ("arm64: dts: sdm845: Set 'bi_tcxo' as ref clock of the DSI PHYs")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210911131922.387964-2-marijn.suijten@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c

index d8128f50b0dd51eabc7c17301da659099078c95a..0b782cc18b3f4b1cf651d96cc4c4d11af8b4ce5c 100644 (file)
@@ -562,7 +562,9 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm, struct clk_hw **prov
        char clk_name[32], parent[32], vco_name[32];
        char parent2[32], parent3[32], parent4[32];
        struct clk_init_data vco_init = {
-               .parent_names = (const char *[]){ "xo" },
+               .parent_data = &(const struct clk_parent_data) {
+                       .fw_name = "ref",
+               },
                .num_parents = 1,
                .name = vco_name,
                .flags = CLK_IGNORE_UNUSED,
index 5b4e991f220d684f3bcc3abb23d9c1df210dbb24..1c1e9861b93f79948559d8a698f837a88d6061a4 100644 (file)
@@ -804,7 +804,9 @@ static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **prov
 {
        char clk_name[32], parent[32], vco_name[32];
        struct clk_init_data vco_init = {
-               .parent_names = (const char *[]){ "xo" },
+               .parent_data = &(const struct clk_parent_data) {
+                       .fw_name = "ref",
+               },
                .num_parents = 1,
                .name = vco_name,
                .flags = CLK_IGNORE_UNUSED,
index 2da673a2add6916fe03b15a15f9ff1ba4df4c569..48eab80b548e1349b2c6dcac0d2cf61c3273e2d1 100644 (file)
@@ -521,7 +521,9 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
 {
        char clk_name[32], parent1[32], parent2[32], vco_name[32];
        struct clk_init_data vco_init = {
-               .parent_names = (const char *[]){ "xo" },
+               .parent_data = &(const struct clk_parent_data) {
+                       .fw_name = "ref", .name = "xo",
+               },
                .num_parents = 1,
                .name = vco_name,
                .flags = CLK_IGNORE_UNUSED,
index 71ed4aa0dc67e6c7ce1707a3094f8be221166395..fc56cdcc9ad6445b22dc4538289c74f20ee7b950 100644 (file)
@@ -385,7 +385,9 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov
 {
        char *clk_name, *parent_name, *vco_name;
        struct clk_init_data vco_init = {
-               .parent_names = (const char *[]){ "pxo" },
+               .parent_data = &(const struct clk_parent_data) {
+                       .fw_name = "ref",
+               },
                .num_parents = 1,
                .flags = CLK_IGNORE_UNUSED,
                .ops = &clk_ops_dsi_pll_28nm_vco,
index cb297b08458e441e3298098b751d39ab46007de8..9f7c408325bad231df359f2b697170f8b88f6ac9 100644 (file)
@@ -590,7 +590,9 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
        char clk_name[32], parent[32], vco_name[32];
        char parent2[32], parent3[32], parent4[32];
        struct clk_init_data vco_init = {
-               .parent_names = (const char *[]){ "bi_tcxo" },
+               .parent_data = &(const struct clk_parent_data) {
+                       .fw_name = "ref",
+               },
                .num_parents = 1,
                .name = vco_name,
                .flags = CLK_IGNORE_UNUSED,