arm64: dts: qcom: sm8150: Add DMA nodes

With this patch, DMA has a chance of probing and doing something
useful.

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Felipe Balbi <felipe.balbi@microsoft.com>
Link: https://lore.kernel.org/r/20210417061951.2105530-3-balbi@kernel.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 51235a9521c24314bc88afb26f909c5c2c949b99..2ebf1512471b433fbdb3d07e41d49c16ce42fc6e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -4,6 +4,7 @@
  * Copyright (c) 2019, Linaro Limited
  */
 
+#include <dt-bindings/dma/qcom-gpi.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/qcom-aoss-qmp.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
@@ -577,6 +578,29 @@
                                 <&sleep_clk>;
                };
 
+               gpi_dma0: dma-controller@800000 {
+                       compatible = "qcom,sm8150-gpi-dma";
+                       reg = <0 0x800000 0 0x60000>;
+                       interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+                       dma-channels = <13>;
+                       dma-channel-mask = <0xfa>;
+                       iommus = <&apps_smmu 0x00d6 0x0>;
+                       #dma-cells = <3>;
+                       status = "disabled";
+               };
+
                qupv3_id_0: geniqup@8c0000 {
                        compatible = "qcom,geni-se-qup";
                        reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -695,6 +719,29 @@
 
                };
 
+               gpi_dma1: dma-controller@a00000 {
+                       compatible = "qcom,sm8150-gpi-dma";
+                       reg = <0 0xa00000 0 0x60000>;
+                       interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+                       dma-channels = <13>;
+                       dma-channel-mask = <0xfa>;
+                       iommus = <&apps_smmu 0x0616 0x0>;
+                       #dma-cells = <3>;
+                       status = "disabled";
+               };
+
                qupv3_id_1: geniqup@ac0000 {
                        compatible = "qcom,geni-se-qup";
                        reg = <0x0 0x00ac0000 0x0 0x6000>;
@@ -795,6 +842,29 @@
                        };
                };
 
+               gpi_dma2: dma-controller@c00000 {
+                       compatible = "qcom,sm8150-gpi-dma";
+                       reg = <0 0xc00000 0 0x60000>;
+                       interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
+                       dma-channels = <13>;
+                       dma-channel-mask = <0xfa>;
+                       iommus = <&apps_smmu 0x07b6 0x0>;
+                       #dma-cells = <3>;
+                       status = "disabled";
+               };
+
                qupv3_id_2: geniqup@cc0000 {
                        compatible = "qcom,geni-se-qup";
                        reg = <0x0 0x00cc0000 0x0 0x6000>;