crypto: ccree - rework cache parameters handling

Rework the setting of DMA cache parameters, program more appropriate
values and explicitly set sharability domain.

Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/ccree/cc_driver.c b/drivers/crypto/ccree/cc_driver.c
index 6f519d3e896ca8e280aa0aadc8a6455cab1af4a4..d0e59e942568a0e7837b4c517559eb56a5df829f 100644 (file)
--- a/drivers/crypto/ccree/cc_driver.c
+++ b/drivers/crypto/ccree/cc_driver.c
@@ -100,6 +100,57 @@ static const struct of_device_id arm_ccree_dev_of_match[] = {
 };
 MODULE_DEVICE_TABLE(of, arm_ccree_dev_of_match);
 
+static void init_cc_cache_params(struct cc_drvdata *drvdata)
+{
+       struct device *dev = drvdata_to_dev(drvdata);
+       u32 cache_params, ace_const, val, mask;
+
+       /* compute CC_AXIM_CACHE_PARAMS */
+       cache_params = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));
+       dev_dbg(dev, "Cache params previous: 0x%08X\n", cache_params);
+
+       /* non cached or write-back, write allocate */
+       val = drvdata->coherent ? 0xb : 0x2;
+
+       mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_AWCACHE);
+       cache_params &= ~mask;
+       cache_params |= FIELD_PREP(mask, val);
+
+       mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_AWCACHE_LAST);
+       cache_params &= ~mask;
+       cache_params |= FIELD_PREP(mask, val);
+
+       mask = CC_GENMASK(CC_AXIM_CACHE_PARAMS_ARCACHE);
+       cache_params &= ~mask;
+       cache_params |= FIELD_PREP(mask, val);
+
+       drvdata->cache_params = cache_params;
+
+       dev_dbg(dev, "Cache params current: 0x%08X\n", cache_params);
+
+       if (drvdata->hw_rev <= CC_HW_REV_710)
+               return;
+
+       /* compute CC_AXIM_ACE_CONST */
+       ace_const = cc_ioread(drvdata, CC_REG(AXIM_ACE_CONST));
+       dev_dbg(dev, "ACE-const previous: 0x%08X\n", ace_const);
+
+       /* system or outer-sharable */
+       val = drvdata->coherent ? 0x2 : 0x3;
+
+       mask = CC_GENMASK(CC_AXIM_ACE_CONST_ARDOMAIN);
+       ace_const &= ~mask;
+       ace_const |= FIELD_PREP(mask, val);
+
+       mask = CC_GENMASK(CC_AXIM_ACE_CONST_AWDOMAIN);
+       ace_const &= ~mask;
+       ace_const |= FIELD_PREP(mask, val);
+
+       dev_dbg(dev, "ACE-const current: 0x%08X\n", ace_const);
+
+       drvdata->ace_const = ace_const;
+}
+
 static u32 cc_read_idr(struct cc_drvdata *drvdata, const u32 *idr_offsets)
 {
        int i;
@@ -218,9 +269,9 @@ bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata)
        return false;
 }
 
-int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe)
+int init_cc_regs(struct cc_drvdata *drvdata)
 {
-       unsigned int val, cache_params;
+       unsigned int val;
        struct device *dev = drvdata_to_dev(drvdata);
 
        /* Unmask all AXI interrupt sources AXI_CFG1 register   */
@@ -245,19 +296,9 @@ int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe)
 
        cc_iowrite(drvdata, CC_REG(HOST_IMR), ~val);
 
-       cache_params = (drvdata->coherent ? CC_COHERENT_CACHE_PARAMS : 0x0);
-
-       val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));
-
-       if (is_probe)
-               dev_dbg(dev, "Cache params previous: 0x%08X\n", val);
-
-       cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), cache_params);
-       val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));
-
-       if (is_probe)
-               dev_dbg(dev, "Cache params current: 0x%08X (expect: 0x%08X)\n",
-                       val, cache_params);
+       cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), drvdata->cache_params);
+       if (drvdata->hw_rev >= CC_HW_REV_712)
+               cc_iowrite(drvdata, CC_REG(AXIM_ACE_CONST), drvdata->ace_const);
 
        return 0;
 }
@@ -445,7 +486,9 @@ static int init_cc_resources(struct platform_device *plat_dev)
        }
        dev_dbg(dev, "Registered to IRQ: %d\n", irq);
 
-       rc = init_cc_regs(new_drvdata, true);
+       init_cc_cache_params(new_drvdata);
+
+       rc = init_cc_regs(new_drvdata);
        if (rc) {
                dev_err(dev, "init_cc_regs failed\n");
                goto post_pm_err;

diff --git a/drivers/crypto/ccree/cc_driver.h b/drivers/crypto/ccree/cc_driver.h
index ed2b2f13a2566481f13978a7135c2852e59c3ea2..5f1d4602eb8f2daa6f106c67b15614c07a54fb24 100644 (file)
--- a/drivers/crypto/ccree/cc_driver.h
+++ b/drivers/crypto/ccree/cc_driver.h
@@ -50,8 +50,6 @@ enum cc_std_body {
        CC_STD_ALL = 0x3
 };
 
-#define CC_COHERENT_CACHE_PARAMS 0xEEE
-
 #define CC_PINS_FULL   0x0
 #define CC_PINS_SLIM   0x9F
 
@@ -156,6 +154,8 @@ struct cc_drvdata {
        int std_bodies;
        bool sec_disabled;
        u32 comp_mask;
+       u32 cache_params;
+       u32 ace_const;
 };
 
 struct cc_crypto_alg {
@@ -206,7 +206,7 @@ static inline void dump_byte_array(const char *name, const u8 *the_array,
 }
 
 bool cc_wait_for_reset_completion(struct cc_drvdata *drvdata);
-int init_cc_regs(struct cc_drvdata *drvdata, bool is_probe);
+int init_cc_regs(struct cc_drvdata *drvdata);
 void fini_cc_regs(struct cc_drvdata *drvdata);
 unsigned int cc_get_default_hash_len(struct cc_drvdata *drvdata);
 

diff --git a/drivers/crypto/ccree/cc_pm.c b/drivers/crypto/ccree/cc_pm.c
index 3c65bf070c908dd672572075faa4a383ae3766de..d5421b0c6831cea100af9f5d7111352124e064ea 100644 (file)
--- a/drivers/crypto/ccree/cc_pm.c
+++ b/drivers/crypto/ccree/cc_pm.c
@@ -45,7 +45,7 @@ static int cc_pm_resume(struct device *dev)
        }
 
        cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_DISABLE);
-       rc = init_cc_regs(drvdata, false);
+       rc = init_cc_regs(drvdata);
        if (rc) {
                dev_err(dev, "init_cc_regs (%x)\n", rc);
                return rc;