drm/amd/display: Filter out YCbCr420 timing if VSC SDP not supported
authorGeorge Shen <george.shen@amd.com>
Fri, 16 Apr 2021 21:35:07 +0000 (17:35 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 10 May 2021 22:06:44 +0000 (18:06 -0400)
[Why]
Per DP specification, YCbCr420 shall use VSC SDP.

[How]
For YCbCr420 timings, fail DP mode timing validation
if DPCD caps do not indicate VSC SDP colorimetry
support.

Signed-off-by: George Shen <george.shen@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Wayne Lin <Wayne.Lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

index ffb4f9027d5e87ddd680f81680e2aa726ebd5dd5..ced552ed7b8a166cc3dbc5c22adaec044edd20b3 100644 (file)
@@ -2411,6 +2411,12 @@ bool dp_validate_mode_timing(
 
        const struct dc_link_settings *link_setting;
 
+       /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */
+       if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 &&
+                       !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED &&
+                       dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL)
+               return false;
+
        /*always DP fail safe mode*/
        if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 &&
                timing->h_addressable == (uint32_t) 640 &&