drm/amdgpu: add hub->ctx_distance in setup_vmid_config
authorYifan Zhang <yifan1.zhang@amd.com>
Thu, 28 Sep 2023 06:02:02 +0000 (14:02 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 9 Oct 2023 20:59:06 +0000 (16:59 -0400)
add hub->ctx_distance when read CONTEXT1_CNTL, align w/
write back operation.

v2: fix coding style errors reported by checkpatch.pl (Christian)

Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Lang Yu <lang.yu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
17 files changed:
drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c
drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c
drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c
drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

index bcb6ba03cead4a7c7acf2c866d21cfeef1a674b6..f9949fedfbb999cfc16ca9ea790edbec04823fa8 100644 (file)
@@ -297,7 +297,7 @@ static void gfxhub_v11_5_0_setup_vmid_config(struct amdgpu_device *adev)
        uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    adev->vm_manager.num_level);
index cdc290a474a927f943ee2eabfedc3a945a5343a3..53a2ba5fcf4ba3c2865b0abcf6a7592f24e4ea10 100644 (file)
@@ -260,7 +260,7 @@ static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
                block_size -= 9;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    num_level);
index ff60670b8464e424a1ca62ea4814883e79ee9a48..55423ff1bb4926d78003ad33dc4b3ceec0591948 100644 (file)
@@ -329,7 +329,8 @@ static void gfxhub_v1_2_xcc_setup_vmid_config(struct amdgpu_device *adev,
        for_each_inst(j, xcc_mask) {
                hub = &adev->vmhub[AMDGPU_GFXHUB(j)];
                for (i = 0; i <= 14; i++) {
-                       tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL, i);
+                       tmp = RREG32_SOC15_OFFSET(GC, GET_INST(GC, j), regVM_CONTEXT1_CNTL,
+                                       i * hub->ctx_distance);
                        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                            num_level);
index 8521c45e8f385cd2eb5cafba9ee855d5221c9d3b..793faf62cb073a82fe23a7b59ae9570b541589be 100644 (file)
@@ -287,7 +287,7 @@ static void gfxhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
        uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    adev->vm_manager.num_level);
index f829c441640aea6c273ed2904ee0a302e849162f..cd0e8a321e460476d36e4c5b82922b7b2ab3cadb 100644 (file)
@@ -296,7 +296,7 @@ static void gfxhub_v2_1_setup_vmid_config(struct amdgpu_device *adev)
        uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    adev->vm_manager.num_level);
index 89ff7910cb0faac1dedd2de4da2c8a85ebb56b58..abe30c8bd2bae40312d6ce49ced08cbadfd4464e 100644 (file)
@@ -294,7 +294,7 @@ static void gfxhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
        uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    adev->vm_manager.num_level);
index be1da59279109c25ecc046eb86c4712c1f4a70ca..b3ef6e71811f3e0ce1973bfbf04a868801279ebe 100644 (file)
@@ -299,7 +299,7 @@ static void gfxhub_v3_0_3_setup_vmid_config(struct amdgpu_device *adev)
        uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(GC, 0, regGCVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, GCVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    adev->vm_manager.num_level);
index fb91b31056cae70585a082cc5f1ee1f92e5a541f..843219a91736093b4b4a6242a75961816d7ec3c4 100644 (file)
@@ -242,7 +242,7 @@ static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
                block_size -= 9;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    num_level);
index 9086f2fdfaf422b4312d47c4fd3096e62cce1e60..92432cd2c0c7b671f06ac536942750746c791f2a 100644 (file)
@@ -274,7 +274,7 @@ static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev)
                block_size -= 9;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    num_level);
index 784c4e07747077b38e758c891fecdedfeb20ac87..2c0419faf8d4919532a8cbd993a2bb0864c3a498 100644 (file)
@@ -344,7 +344,7 @@ static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
                hub = &adev->vmhub[AMDGPU_MMHUB0(j)];
                for (i = 0; i <= 14; i++) {
                        tmp = RREG32_SOC15_OFFSET(MMHUB, j, regVM_CONTEXT1_CNTL,
-                                                 i);
+                                                 i * hub->ctx_distance);
                        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
                                            ENABLE_CONTEXT, 1);
                        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
index 37458f906980cf6b9b231ec1501dba7bb921b680..02fd45261399cc9dfe31c7d2f636d6bb8cb8dd1f 100644 (file)
@@ -367,7 +367,7 @@ static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
        uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    adev->vm_manager.num_level);
index 4ddd9448e2bc1c1a9a63404e6767832541bde720..5eb8122e27469c1fc3b28a4ac79a96ba92a5ed55 100644 (file)
@@ -285,7 +285,7 @@ static void mmhub_v2_3_setup_vmid_config(struct amdgpu_device *adev)
        uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    adev->vm_manager.num_level);
index 9627df8b194ba57f1f3679a7272e07b176436ff0..7d5242df58a511c6b77fc5af1bb1d53d97c481dc 100644 (file)
@@ -323,7 +323,7 @@ static void mmhub_v3_0_setup_vmid_config(struct amdgpu_device *adev)
        uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    adev->vm_manager.num_level);
index 77bff803b45222785a812fdbbd3d55d290fc21ae..134c4ec1088785c0c9886f94e0fa2f915bcc903d 100644 (file)
@@ -310,7 +310,7 @@ static void mmhub_v3_0_1_setup_vmid_config(struct amdgpu_device *adev)
        uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    adev->vm_manager.num_level);
index d1fc9dce7151954a5a4bd0c990daa9f201989f7d..f0f182f033b9883c2d8866debc4a2165d871cbf6 100644 (file)
@@ -315,7 +315,7 @@ static void mmhub_v3_0_2_setup_vmid_config(struct amdgpu_device *adev)
        uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    adev->vm_manager.num_level);
index 3d80a184ce6b52349dc74adad3a785ba780df9a3..76b12f015d1d1a0130bd4c9b45d9d405f240b3b6 100644 (file)
@@ -303,7 +303,7 @@ static void mmhub_v3_3_setup_vmid_config(struct amdgpu_device *adev)
        uint32_t tmp;
 
        for (i = 0; i <= 14; i++) {
-               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i);
+               tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regMMVM_CONTEXT1_CNTL, i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
                                    adev->vm_manager.num_level);
index 5718e4d40e6665e1014bc5bd7536e421bc2cff58..1b7da4aff2b8f8e7e2771a6bfba9c6fb373cb623 100644 (file)
@@ -308,7 +308,7 @@ static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
 
        for (i = 0; i <= 14; i++) {
                tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
-                               hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
+                               hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i * hub->ctx_distance);
                tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
                                    ENABLE_CONTEXT, 1);
                tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,