drm/amdgpu: add clock gating DPG mode for VCN3.0

Add vcn_v3_0_clock_gating_dpg_mode to enabling clock gating in DPG mode for VCN3.0

V2: Separate from previous patch-0002, and update description.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: James Zhu <james.zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index 340cb344a35d250748dcd8d5d62010bf9ee413a2..b0fc589ac88f92ce184b8d366a38bc130453eeee 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -613,6 +613,54 @@ static void vcn_v3_0_disable_clock_gating(struct amdgpu_device *adev, int inst)
        WREG32_SOC15(VCN, inst, mmUVD_SUVD_CGC_CTRL, data);
 }
 
+static void vcn_v3_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
+               uint8_t sram_sel, int inst_idx, uint8_t indirect)
+{
+       uint32_t reg_data = 0;
+
+       /* enable sw clock gating control */
+       if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
+               reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+       else
+               reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
+       reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
+       reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
+       reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
+                UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
+                UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
+                UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
+                UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
+                UVD_CGC_CTRL__SYS_MODE_MASK |
+                UVD_CGC_CTRL__UDEC_MODE_MASK |
+                UVD_CGC_CTRL__MPEG2_MODE_MASK |
+                UVD_CGC_CTRL__REGS_MODE_MASK |
+                UVD_CGC_CTRL__RBC_MODE_MASK |
+                UVD_CGC_CTRL__LMI_MC_MODE_MASK |
+                UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
+                UVD_CGC_CTRL__IDCT_MODE_MASK |
+                UVD_CGC_CTRL__MPRD_MODE_MASK |
+                UVD_CGC_CTRL__MPC_MODE_MASK |
+                UVD_CGC_CTRL__LBSI_MODE_MASK |
+                UVD_CGC_CTRL__LRBBM_MODE_MASK |
+                UVD_CGC_CTRL__WCB_MODE_MASK |
+                UVD_CGC_CTRL__VCPU_MODE_MASK |
+                UVD_CGC_CTRL__MMSCH_MODE_MASK);
+       WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
+               VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
+
+       /* turn off clock gating */
+       WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
+               VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
+
+       /* turn on SUVD clock gating */
+       WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
+               VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
+
+       /* turn on sw mode in UVD_SUVD_CGC_CTRL */
+       WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
+               VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
+}
+
 /**
  * vcn_v3_0_enable_clock_gating - enable VCN clock gating
  *