mtd: rawnand: qcom: Update register macro name for 0x2c offset

This change will remove unused register name macro NAND_DEV1_ECC_CFG.
Since this register was only available in QPIC version 1.4.20 ipq40xx
and it was not used. In QPIC version 1.5 on wards this register got
removed.In QPIC version 2.0 0x2c offset is updated with register
NAND_AUTO_STATUS_EN So adding this register macro NAND_AUTO_STATUS_EN
with offset 0x2c.

Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/1612037236-7954-1-git-send-email-mdalam@codeaurora.org

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index fd4c318b520f3673cd20215b5b8c910fd03ce5d6..c0d3f92042235d45e73ea5df464f4ea010fa7ad9 100644 (file)
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -27,7 +27,7 @@
 #define        NAND_DEV0_CFG0                  0x20
 #define        NAND_DEV0_CFG1                  0x24
 #define        NAND_DEV0_ECC_CFG               0x28
-#define        NAND_DEV1_ECC_CFG               0x2c
+#define        NAND_AUTO_STATUS_EN             0x2c
 #define        NAND_DEV1_CFG0                  0x30
 #define        NAND_DEV1_CFG1                  0x34
 #define        NAND_READ_ID                    0x40