perf/x86/intel/uncore: Add Sapphire Rapids server PCU support

The PCU is the primary power controller for the Sapphire Rapids.

Except the name, all the information can be retrieved from the discovery
tables.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-7-git-send-email-kan.liang@linux.intel.com

diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 890a98279fca1dde801fc0912a0dd8a65299ab19..913cd7aca65de3724d2f9baa020bd97bea5fe9ae 100644 (file)
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -5633,6 +5633,10 @@ static struct intel_uncore_type spr_uncore_m2pcie = {
        .name                   = "m2pcie",
 };
 
+static struct intel_uncore_type spr_uncore_pcu = {
+       .name                   = "pcu",
+};
+
 #define UNCORE_SPR_NUM_UNCORE_TYPES            12
 
 static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
@@ -5640,7 +5644,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
        &spr_uncore_iio,
        &spr_uncore_irp,
        &spr_uncore_m2pcie,
-       NULL,
+       &spr_uncore_pcu,
        NULL,
        NULL,
        NULL,