octeon_ep: support OCTEON CN98 devices
authorShinas Rasheed <srasheed@marvell.com>
Wed, 29 Nov 2023 04:53:48 +0000 (20:53 -0800)
committerJakub Kicinski <kuba@kernel.org>
Fri, 1 Dec 2023 07:17:04 +0000 (23:17 -0800)
Add PCI Endpoint NIC support for Octeon CN98 devices.
CN98 devices are part of Octeon 9 family products with
similar PCI NIC characteristics to CN93, already supported
driver.

Add CN98 card to the device id table, as well
as support differences in the register fields and
certain usage scenarios such as unload.

Signed-off-by: Shinas Rasheed <srasheed@marvell.com>
Link: https://lore.kernel.org/r/20231129045348.2538843-3-srasheed@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Documentation/networking/device_drivers/ethernet/marvell/octeon_ep.rst
drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c
drivers/net/ethernet/marvell/octeon_ep/octep_main.c
drivers/net/ethernet/marvell/octeon_ep/octep_main.h
drivers/net/ethernet/marvell/octeon_ep/octep_regs_cn9k_pf.h

index 613a818d5db6eccffa003f07c04cabb740c2c82c..c96d262b30beef798a092640551e0e55faaae855 100644 (file)
@@ -22,6 +22,7 @@ EndPoint NIC.
 Supported Devices
 =================
 Currently, this driver support following devices:
+ * Network controller: Cavium, Inc. Device b100
  * Network controller: Cavium, Inc. Device b200
  * Network controller: Cavium, Inc. Device b400
  * Network controller: Cavium, Inc. Device b900
index d4ee2454675b6cdb873bdaba37db051053fbb128..8baabd07e91f40d76ecd52f9a07ada99ec20876c 100644 (file)
@@ -216,9 +216,15 @@ static void octep_init_config_cn93_pf(struct octep_device *oct)
        conf->sriov_cfg.vf_srn = CN93_SDP_EPF_RINFO_SRN(val);
 
        val = octep_read_csr64(oct, CN93_SDP_MAC_PF_RING_CTL(oct->pcie_port));
-       conf->pf_ring_cfg.srn =  CN93_SDP_MAC_PF_RING_CTL_SRN(val);
-       conf->pf_ring_cfg.max_io_rings = CN93_SDP_MAC_PF_RING_CTL_RPPF(val);
-       conf->pf_ring_cfg.active_io_rings = conf->pf_ring_cfg.max_io_rings;
+       if (oct->chip_id == OCTEP_PCI_DEVICE_ID_CN98_PF) {
+               conf->pf_ring_cfg.srn =  CN98_SDP_MAC_PF_RING_CTL_SRN(val);
+               conf->pf_ring_cfg.max_io_rings = CN98_SDP_MAC_PF_RING_CTL_RPPF(val);
+               conf->pf_ring_cfg.active_io_rings = conf->pf_ring_cfg.max_io_rings;
+       } else {
+               conf->pf_ring_cfg.srn =  CN93_SDP_MAC_PF_RING_CTL_SRN(val);
+               conf->pf_ring_cfg.max_io_rings = CN93_SDP_MAC_PF_RING_CTL_RPPF(val);
+               conf->pf_ring_cfg.active_io_rings = conf->pf_ring_cfg.max_io_rings;
+       }
        dev_info(&pdev->dev, "pf_srn=%u rpvf=%u nvfs=%u rppf=%u\n",
                 conf->pf_ring_cfg.srn, conf->sriov_cfg.active_rings_per_vf,
                 conf->sriov_cfg.active_vfs, conf->pf_ring_cfg.active_io_rings);
@@ -578,6 +584,13 @@ static irqreturn_t octep_ioq_intr_handler_cn93_pf(void *data)
        return IRQ_HANDLED;
 }
 
+/* soft reset of 98xx */
+static int octep_soft_reset_cn98_pf(struct octep_device *oct)
+{
+       dev_info(&oct->pdev->dev, "CN98XX: skip soft reset\n");
+       return 0;
+}
+
 /* soft reset of 93xx */
 static int octep_soft_reset_cn93_pf(struct octep_device *oct)
 {
@@ -806,7 +819,10 @@ void octep_device_setup_cn93_pf(struct octep_device *oct)
        oct->hw_ops.misc_intr_handler = octep_misc_intr_handler_cn93_pf;
        oct->hw_ops.rsvd_intr_handler = octep_rsvd_intr_handler_cn93_pf;
        oct->hw_ops.ioq_intr_handler = octep_ioq_intr_handler_cn93_pf;
-       oct->hw_ops.soft_reset = octep_soft_reset_cn93_pf;
+       if (oct->chip_id == OCTEP_PCI_DEVICE_ID_CN98_PF)
+               oct->hw_ops.soft_reset = octep_soft_reset_cn98_pf;
+       else
+               oct->hw_ops.soft_reset = octep_soft_reset_cn93_pf;
        oct->hw_ops.reinit_regs = octep_reinit_regs_cn93_pf;
 
        oct->hw_ops.enable_interrupts = octep_enable_interrupts_cn93_pf;
index 423eec5ff3ad5a7abeb6ad49678cf610c56676bd..1a24b3d3cce6b5e7db77144f7f71a945a6c99c69 100644 (file)
@@ -22,6 +22,7 @@ struct workqueue_struct *octep_wq;
 
 /* Supported Devices */
 static const struct pci_device_id octep_pci_id_tbl[] = {
+       {PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CN98_PF)},
        {PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CN93_PF)},
        {PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CNF95N_PF)},
        {PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OCTEP_PCI_DEVICE_ID_CN10KA_PF)},
@@ -1147,6 +1148,8 @@ static void octep_ctrl_mbox_task(struct work_struct *work)
 static const char *octep_devid_to_str(struct octep_device *oct)
 {
        switch (oct->chip_id) {
+       case OCTEP_PCI_DEVICE_ID_CN98_PF:
+               return "CN98XX";
        case OCTEP_PCI_DEVICE_ID_CN93_PF:
                return "CN93XX";
        case OCTEP_PCI_DEVICE_ID_CNF95N_PF:
@@ -1197,6 +1200,7 @@ int octep_device_setup(struct octep_device *oct)
        dev_info(&pdev->dev, "chip_id = 0x%x\n", pdev->device);
 
        switch (oct->chip_id) {
+       case OCTEP_PCI_DEVICE_ID_CN98_PF:
        case OCTEP_PCI_DEVICE_ID_CN93_PF:
        case OCTEP_PCI_DEVICE_ID_CNF95N_PF:
                dev_info(&pdev->dev, "Setting up OCTEON %s PF PASS%d.%d\n",
index e2fe8b28eb0ec855a3efb7d3e072ad44580274d6..e1b4b2af618edd737e5105cfbe0e9cdece498fba 100644 (file)
@@ -18,6 +18,7 @@
 #define  OCTEP_PCIID_CN93_PF  0xB200177d
 #define  OCTEP_PCIID_CN93_VF  0xB203177d
 
+#define  OCTEP_PCI_DEVICE_ID_CN98_PF 0xB100
 #define  OCTEP_PCI_DEVICE_ID_CN93_PF 0xB200
 #define  OCTEP_PCI_DEVICE_ID_CN93_VF 0xB203
 
index 0a43983e910155a16dff83f3bb435086e710e89d..2e20a39d89aff26f84515002abfbd8ace852238f 100644 (file)
 #define    CN93_SDP_MAC_PF_RING_CTL_SRN(val)   (((val) >> 8) & 0xFF)
 #define    CN93_SDP_MAC_PF_RING_CTL_RPPF(val)  (((val) >> 16) & 0x3F)
 
+#define    CN98_SDP_MAC_PF_RING_CTL_NPFS(val)  (((val) >> 48) & 0xF)
+#define    CN98_SDP_MAC_PF_RING_CTL_SRN(val)   ((val) & 0xFF)
+#define    CN98_SDP_MAC_PF_RING_CTL_RPPF(val)  (((val) >> 32) & 0x3F)
+
 /* Number of non-queue interrupts in CN93xx */
 #define    CN93_NUM_NON_IOQ_INTR    16