drm/amd/display: Power down hardware if timer not trigger

[WHY]
In headless systems, if SetMode/Power down timer
is not called, hardware will not be powered down
causing HW/SW discrepancies. Powering down hardware
on SetPowerState to D3 will ensure SW/HW state is accurate.

[HOW]
If PowerDownThread timer is not trigger but OS call
SetPowerState to D3, power down hardware.

Reviewed-by: Eric Yang <Eric.Yang2@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index 59fdd7f0d60946581358c3b68a7febd11890f303..969b402504342cd8e39ab09153820b138d577b4d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -615,13 +615,37 @@ static void dcn31_clk_mgr_helper_populate_bw_params(struct clk_mgr_internal *clk
        }
 }
 
+void dcn31_set_low_power_state(struct clk_mgr *clk_mgr_base)
+{
+       int display_count;
+       struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+       struct dc *dc = clk_mgr_base->ctx->dc;
+       struct dc_state *context = dc->current_state;
+
+       if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
+               display_count = dcn31_get_active_display_cnt_wa(dc, context);
+               /* if we can go lower, go lower */
+               if (display_count == 0) {
+                       union display_idle_optimization_u idle_info = { 0 };
+
+                       idle_info.idle_info.df_request_disabled = 1;
+                       idle_info.idle_info.phy_ref_clk_off = 1;
+                       idle_info.idle_info.s0i2_rdy = 1;
+                       dcn31_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
+                       /* update power state */
+                       clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
+               }
+       }
+}
+
 static struct clk_mgr_funcs dcn31_funcs = {
        .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
        .update_clocks = dcn31_update_clocks,
        .init_clocks = dcn31_init_clocks,
        .enable_pme_wa = dcn31_enable_pme_wa,
        .are_clock_states_equal = dcn31_are_clock_states_equal,
-       .notify_wm_ranges = dcn31_notify_wm_ranges
+       .notify_wm_ranges = dcn31_notify_wm_ranges,
+       .set_low_power_state = dcn31_set_low_power_state
 };
 extern struct clk_mgr_funcs dcn3_fpga_funcs;