drm/i915/display: Add 480 MHz CDCLK steps for RPL-U

A new step of 480MHz has been added on SKUs that have a RPL-U
device id to support 120Hz displays more efficiently. Use a
new quirk to identify the machine for which this change needs
to be applied.

v2: (Matt)
    - Add missing clock steps
    - Correct reference clock typo

v3: - Revert to RPL-U subplatform (Jani)

v4: - Remove Bspec reference from code (Jani)

Bspec: 55409
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230130100806.1373883-3-chaitanya.kumar.borah@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 82da76b586edbada87d32b1514cf33d5e7b1803d..084a483f97766165472c2f6b4fb71f57e2b07c00 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1329,6 +1329,30 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
        {}
 };
 
+static const struct intel_cdclk_vals rplu_cdclk_table[] = {
+       { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
+       { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
+       { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+       { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
+       { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+       { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+       { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
+       { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
+       { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+       { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
+       { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+       { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+       { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
+       { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
+       { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+       { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
+       { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+       { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+       {}
+};
+
 static const struct intel_cdclk_vals dg2_cdclk_table[] = {
        { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
        { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
@@ -3364,6 +3388,8 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
                /* Wa_22011320316:adl-p[a0] */
                if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
                        dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
+               else if (IS_ADLP_RPLU(dev_priv))
+                       dev_priv->display.cdclk.table = rplu_cdclk_table;
                else
                        dev_priv->display.cdclk.table = adlp_cdclk_table;
        } else if (IS_ROCKETLAKE(dev_priv)) {