drm/i915/dg2: Tile 4 plane format support

Tile4 in bspec format is 4K tile organized into
64B subtiles with same basic shape as for legacy TileY
which will be supported by Display13.

v2: - Moved Tile4 associating struct for modifier/display to
      the beginning(Imre Deak)
    - Removed unneeded case I915_FORMAT_MOD_4_TILED modifier
      checks(Imre Deak)
    - Fixed I915_FORMAT_MOD_4_TILED to be 9 instead of 12
      (Imre Deak)

v3: - Rebased patch on top of new changes related to plane_caps.
    - Added static assert to check that PLANE_CTL_TILING_YF
      matches PLANE_CTL_TILING_4(Nanley Chery)
    - Fixed naming and layout description for Tile 4 in drm uapi
      header(Nanley Chery)

v4: - Extracted drm_fourcc changes to separate patch(Nanley Chery)

Reviewed-by: Imre Deak <imre.deak@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220118115544.15116-3-stanislav.lisovskiy@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 80b19c304c4325179e55b5f8c96bf13a3b2459be..7bf24df20b14a276e5e27f318d8018d28525a5bc 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7458,6 +7458,7 @@ static int intel_atomic_check_async(struct intel_atomic_state *state, struct int
                case I915_FORMAT_MOD_X_TILED:
                case I915_FORMAT_MOD_Y_TILED:
                case I915_FORMAT_MOD_Yf_TILED:
+               case I915_FORMAT_MOD_4_TILED:
                        break;
                default:
                        drm_dbg_kms(&i915->drm,

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 23cfe2e5ce2a4ff2ee4694c9c1ee13ee52569b6d..94c57facbb463b8e6cc2863a9f5a2e965d909f3e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -135,11 +135,16 @@ struct intel_modifier_desc {
                                         INTEL_PLANE_CAP_CCS_MC)
 #define INTEL_PLANE_CAP_TILING_MASK    (INTEL_PLANE_CAP_TILING_X | \
                                         INTEL_PLANE_CAP_TILING_Y | \
-                                        INTEL_PLANE_CAP_TILING_Yf)
+                                        INTEL_PLANE_CAP_TILING_Yf | \
+                                        INTEL_PLANE_CAP_TILING_4)
 #define INTEL_PLANE_CAP_TILING_NONE    0
 
 static const struct intel_modifier_desc intel_modifiers[] = {
        {
+               .modifier = I915_FORMAT_MOD_4_TILED,
+               .display_ver = { 13, 13 },
+               .plane_caps = INTEL_PLANE_CAP_TILING_4,
+       }, {
                .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS,
                .display_ver = { 12, 13 },
                .plane_caps = INTEL_PLANE_CAP_TILING_Y | INTEL_PLANE_CAP_CCS_MC,
@@ -545,6 +550,12 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
                        return 128;
                else
                        return 512;
+       case I915_FORMAT_MOD_4_TILED:
+               /*
+                * Each 4K tile consists of 64B(8*8) subtiles, with
+                * same shape as Y Tile(i.e 4*16B OWords)
+                */
+               return 128;
        case I915_FORMAT_MOD_Y_TILED_CCS:
                if (intel_fb_is_ccs_aux_plane(fb, color_plane))
                        return 128;
@@ -650,6 +661,7 @@ static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier)
                return I915_TILING_Y;
        case INTEL_PLANE_CAP_TILING_X:
                return I915_TILING_X;
+       case INTEL_PLANE_CAP_TILING_4:
        case INTEL_PLANE_CAP_TILING_Yf:
        case INTEL_PLANE_CAP_TILING_NONE:
                return I915_TILING_NONE;
@@ -737,6 +749,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
        case I915_FORMAT_MOD_Y_TILED_CCS:
        case I915_FORMAT_MOD_Yf_TILED_CCS:
        case I915_FORMAT_MOD_Y_TILED:
+       case I915_FORMAT_MOD_4_TILED:
        case I915_FORMAT_MOD_Yf_TILED:
                return 1 * 1024 * 1024;
        default:

diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h
index ba9df8986c1ee7237674f24b551041f1744582e7..12386f13a4e0f4f382ab160f0ffc9e8cbb6cf56e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fb.h
+++ b/drivers/gpu/drm/i915/display/intel_fb.h
@@ -27,6 +27,7 @@ struct intel_plane_state;
 #define INTEL_PLANE_CAP_TILING_X       BIT(3)
 #define INTEL_PLANE_CAP_TILING_Y       BIT(4)
 #define INTEL_PLANE_CAP_TILING_Yf      BIT(5)
+#define INTEL_PLANE_CAP_TILING_4       BIT(6)
 
 bool intel_fb_is_ccs_modifier(u64 modifier);
 bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier);

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 87f4af3fd523ec0d1a9a2191aeec6bbd422c43db..f7dca327c29492be03bed02ccfd50f31ee277389 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -946,6 +946,7 @@ static bool tiling_is_valid(const struct intel_plane_state *plane_state)
        case I915_FORMAT_MOD_Y_TILED:
        case I915_FORMAT_MOD_Yf_TILED:
                return DISPLAY_VER(i915) >= 9;
+       case I915_FORMAT_MOD_4_TILED:
        case I915_FORMAT_MOD_X_TILED:
                return true;
        default:

diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index d7b1de4cc205ef3407d89004b25a61c732dbefad..e207d12286b5ab3391b222d6b7de955441407348 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -127,6 +127,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
        case DRM_FORMAT_MOD_LINEAR:
        case I915_FORMAT_MOD_X_TILED:
        case I915_FORMAT_MOD_Y_TILED:
+       case I915_FORMAT_MOD_4_TILED:
                break;
        default:
                drm_dbg(&dev_priv->drm,

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 1223075595ff0bc782e2ae75e1941c9ad66b90ba..5299dfe688024c47ee336444db5c95528fabc1d4 100644 (file)
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -762,6 +762,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
                return PLANE_CTL_TILED_X;
        case I915_FORMAT_MOD_Y_TILED:
                return PLANE_CTL_TILED_Y;
+       case I915_FORMAT_MOD_4_TILED:
+               return PLANE_CTL_TILED_4;
        case I915_FORMAT_MOD_Y_TILED_CCS:
        case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
                return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -2011,9 +2013,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
        case DRM_FORMAT_Y216:
        case DRM_FORMAT_XVYU12_16161616:
        case DRM_FORMAT_XVYU16161616:
-               if (modifier == DRM_FORMAT_MOD_LINEAR ||
-                   modifier == I915_FORMAT_MOD_X_TILED ||
-                   modifier == I915_FORMAT_MOD_Y_TILED)
+               if (!intel_fb_is_ccs_modifier(modifier))
                        return true;
                fallthrough;
        default:
@@ -2106,6 +2106,8 @@ static u8 skl_get_plane_caps(struct drm_i915_private *i915,
                caps |= INTEL_PLANE_CAP_TILING_Y;
        if (DISPLAY_VER(i915) < 12)
                caps |= INTEL_PLANE_CAP_TILING_Yf;
+       if (HAS_4TILE(i915))
+               caps |= INTEL_PLANE_CAP_TILING_4;
 
        if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) {
                caps |= INTEL_PLANE_CAP_CCS_RC;
@@ -2278,6 +2280,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
        unsigned int aligned_height;
        struct drm_framebuffer *fb;
        struct intel_framebuffer *intel_fb;
+       static_assert(PLANE_CTL_TILED_YF == PLANE_CTL_TILED_4);
 
        if (!plane->get_hw_state(plane, &pipe))
                return;
@@ -2340,11 +2343,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
                else
                        fb->modifier = I915_FORMAT_MOD_Y_TILED;
                break;
-       case PLANE_CTL_TILED_YF:
-               if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
-                       fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
-               else
-                       fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+       case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
+               if (HAS_4TILE(dev_priv)) {
+                       fb->modifier = I915_FORMAT_MOD_4_TILED;
+               } else {
+                       if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+                               fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
+                       else
+                               fb->modifier = I915_FORMAT_MOD_Yf_TILED;
+               }
                break;
        default:
                MISSING_CASE(tiling);

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f600d1cb01b34b598f9d0b6b8df80c1ad10902a5..e71dcd2701ca483cfa9611ae0e293691d6b1cf1c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1252,6 +1252,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define CMDPARSER_USES_GGTT(dev_priv) (GRAPHICS_VER(dev_priv) == 7)
 
 #define HAS_LLC(dev_priv)      (INTEL_INFO(dev_priv)->has_llc)
+#define HAS_4TILE(dev_priv)    (INTEL_INFO(dev_priv)->has_4tile)
 #define HAS_SNOOP(dev_priv)    (INTEL_INFO(dev_priv)->has_snoop)
 #define HAS_EDRAM(dev_priv)    ((dev_priv)->edram_size_mb)
 #define HAS_SECURE_BATCHES(dev_priv) (GRAPHICS_VER(dev_priv) < 6)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 8246cbe9b01db92ada9cae93ca3128270d32f018..a95ae08b071c50f138033b1c930ebf752be07657 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1046,6 +1046,7 @@ static const struct intel_device_info dg2_info = {
        DGFX_FEATURES,
        .graphics.rel = 55,
        .media.rel = 55,
+       .has_4tile = 1,
        PLATFORM(INTEL_DG2),
        .has_guc_deprivilege = 1,
        .has_64k_pages = 1,

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2b8a3086ed35aad70999a213e48eceb23228a503..5f6c307f476a33db8280c26d6200fd069f01eb22 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4844,6 +4844,7 @@
 #define   PLANE_CTL_TILED_X                    REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1)
 #define   PLANE_CTL_TILED_Y                    REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4)
 #define   PLANE_CTL_TILED_YF                   REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
+#define   PLANE_CTL_TILED_4                     REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5)
 #define   PLANE_CTL_ASYNC_FLIP                 REG_BIT(9)
 #define   PLANE_CTL_FLIP_HORIZONTAL            REG_BIT(8)
 #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 27dcfe6f24290f9faefdf2daa2092abf041698db..8026e805ff12b6369f8894b4468190991a74151f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -133,6 +133,7 @@ enum intel_ppgtt_type {
        func(has_64k_pages); \
        func(gpu_reset_clobbers_display); \
        func(has_reset_engine); \
+       func(has_4tile); \
        func(has_global_mocs); \
        func(has_gt_uc); \
        func(has_guc_deprivilege); \

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5af16ca4dabd6e8ebd77e41e44745e8862548f40..51308211618e95be95825fe4e06ff8e6fd6ad05d 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5415,6 +5415,7 @@ skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
        }
 
        wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED ||
+                     modifier == I915_FORMAT_MOD_4_TILED ||
                      modifier == I915_FORMAT_MOD_Yf_TILED ||
                      modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
                      modifier == I915_FORMAT_MOD_Yf_TILED_CCS;