Add a new optional input reference clock (pll1_refclk) for PLL1.
Update bindings to support dual reference clock multilink configurations.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240104133013.2911035-2-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
minItems: 1
maxItems: 2
description:
- PHY reference clock for 1 item. Must contain an entry in clock-names.
- Optional Parent to enable output reference clock.
+ PHY input reference clocks - refclk (for PLL0) & pll1_refclk (for PLL1).
+ pll1_refclk is optional and used for multi-protocol configurations requiring
+ separate reference clock for each protocol.
+ Same refclk is used for both PLL0 and PLL1 if no separate pll1_refclk is used.
+ Optional parent clock (phy_en_refclk) to enable a reference clock output feature
+ on some platforms to output either derived or received reference clock.
clock-names:
minItems: 1
items:
- const: refclk
- - const: phy_en_refclk
+ - enum: [ pll1_refclk, phy_en_refclk ]
reg:
minItems: 1