dmaengine: dw: Convert members to u32 in platform data

u32 is a type that is used for properties retrieval from DT.
With the type change it allows to clean up properties reading routine.

While at it, order the fields in way how they are parsed.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
Tested-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/r/20210802184355.49879-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index b11b0c8bc5da01270b0ed9e5517a524e1b2074a3..860ba4bc5eadecdae44b60d004c7272a06b48573 100644 (file)
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -41,11 +41,11 @@ struct dw_dma_slave {
 
 /**
  * struct dw_dma_platform_data - Controller configuration parameters
+ * @nr_masters: Number of AHB masters supported by the controller
  * @nr_channels: Number of channels supported by hardware (max 8)
  * @chan_allocation_order: Allocate channels starting from 0 or 7
  * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
  * @block_size: Maximum block size supported by the controller
- * @nr_masters: Number of AHB masters supported by the controller
  * @data_width: Maximum data width supported by hardware per AHB master
  *             (in bytes, power of 2)
  * @multi_block: Multi block transfers supported by hardware per channel.
@@ -55,25 +55,25 @@ struct dw_dma_slave {
  * @quirks: Optional platform quirks.
  */
 struct dw_dma_platform_data {
-       unsigned int    nr_channels;
+       u32             nr_masters;
+       u32             nr_channels;
 #define CHAN_ALLOCATION_ASCENDING      0       /* zero to seven */
 #define CHAN_ALLOCATION_DESCENDING     1       /* seven to zero */
-       unsigned char   chan_allocation_order;
+       u32             chan_allocation_order;
 #define CHAN_PRIORITY_ASCENDING                0       /* chan0 highest */
 #define CHAN_PRIORITY_DESCENDING       1       /* chan7 highest */
-       unsigned char   chan_priority;
-       unsigned int    block_size;
-       unsigned char   nr_masters;
-       unsigned char   data_width[DW_DMA_MAX_NR_MASTERS];
-       unsigned char   multi_block[DW_DMA_MAX_NR_CHANNELS];
+       u32             chan_priority;
+       u32             block_size;
+       u32             data_width[DW_DMA_MAX_NR_MASTERS];
+       u32             multi_block[DW_DMA_MAX_NR_CHANNELS];
        u32             max_burst[DW_DMA_MAX_NR_CHANNELS];
 #define CHAN_PROTCTL_PRIVILEGED                BIT(0)
 #define CHAN_PROTCTL_BUFFERABLE                BIT(1)
 #define CHAN_PROTCTL_CACHEABLE         BIT(2)
 #define CHAN_PROTCTL_MASK              GENMASK(2, 0)
-       unsigned char   protctl;
+       u32             protctl;
 #define DW_DMA_QUIRK_XBAR_PRESENT      BIT(0)
-       unsigned int    quirks;
+       u32             quirks;
 };
 
 #endif /* _PLATFORM_DATA_DMA_DW_H */