arm64: dts: renesas: r8a779g0: Add missing SCIF_CLK2

R-Car V4H actually has two SCIF_CLK pins.
The second pin provides the SCIF_CLK signal for HSCIF2 and SCIF4.

Fixes: a4c31c56d2d35641 ("arm64: dts: renesas: r8a779g0: Add SCIF nodes")
Fixes: 39d9dfc6fbe1860e ("arm64: dts: renesas: r8a779g0: Add remaining HSCIF nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/72f20c1bf32187bd30a963cafe27252907d661f9.1705589612.git.geert+renesas@glider.be

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 3be1159982b204e9a72ee056e0f4e6267d46de13..0c83940b3d8a1088ed54cb08553dd8d443aa2fa9 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -185,13 +185,19 @@
                method = "smc";
        };
 
-       /* External SCIF clock - to be overridden by boards that provide it */
+       /* External SCIF clocks - to be overridden by boards that provide them */
        scif_clk: scif {
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <0>;
        };
 
+       scif_clk2: scif2 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <0>;
+       };
+
        soc: soc {
                compatible = "simple-bus";
                interrupt-parent = <&gic>;
@@ -681,7 +687,7 @@
                        interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 516>,
                                 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
-                                <&scif_clk>;
+                                <&scif_clk2>;
                        clock-names = "fck", "brg_int", "scif_clk";
                        dmas = <&dmac0 0x35>, <&dmac0 0x34>,
                               <&dmac1 0x35>, <&dmac1 0x34>;
@@ -1057,7 +1063,7 @@
                        interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 705>,
                                 <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>,
-                                <&scif_clk>;
+                                <&scif_clk2>;
                        clock-names = "fck", "brg_int", "scif_clk";
                        dmas = <&dmac0 0x59>, <&dmac0 0x58>,
                               <&dmac1 0x59>, <&dmac1 0x58>;