{
}
-static inline int cpu_halted(CPUState *env) {
+static inline int cpu_halted(CPUState *env)
+{
if (!env->halted)
return 0;
if (env->interrupt_request &
return EXCP_HALTED;
}
+static inline void compute_hflags(CPUState *env)
+{
+ env->hflags &= ~(MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | MIPS_HFLAG_F64 |
+ MIPS_HFLAG_FPU | MIPS_HFLAG_UM);
+ if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
+ !(env->CP0_Status & (1 << CP0St_ERL)) &&
+ !(env->hflags & MIPS_HFLAG_DM) &&
+ (env->CP0_Status & (1 << CP0St_UM)))
+ env->hflags |= MIPS_HFLAG_UM;
+#ifdef TARGET_MIPS64
+ if (!(env->hflags & MIPS_HFLAG_UM) ||
+ (env->CP0_Status & (1 << CP0St_PX)) ||
+ (env->CP0_Status & (1 << CP0St_UX)))
+ env->hflags |= MIPS_HFLAG_64;
+#endif
+ if ((env->CP0_Status & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_UM))
+ env->hflags |= MIPS_HFLAG_CP0;
+ if (env->CP0_Status & (1 << CP0St_CU1))
+ env->hflags |= MIPS_HFLAG_FPU;
+ if (env->CP0_Status & (1 << CP0St_FR))
+ env->hflags |= MIPS_HFLAG_F64;
+}
+
#endif /* !defined(__QEMU_MIPS_EXEC_H__) */
env->CP0_DEPC = env->PC[env->current_tc];
}
enter_debug_mode:
- env->hflags |= MIPS_HFLAG_DM;
- env->hflags |= MIPS_HFLAG_64;
+ env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
env->hflags &= ~MIPS_HFLAG_UM;
- env->hflags |= MIPS_HFLAG_CP0;
/* EJTAG probe trap enable is not implemented... */
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->CP0_ErrorEPC = env->PC[env->current_tc];
}
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
- env->hflags |= MIPS_HFLAG_64;
+ env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
env->hflags &= ~MIPS_HFLAG_UM;
- env->hflags |= MIPS_HFLAG_CP0;
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->PC[env->current_tc] = (int32_t)0xBFC00000;
env->CP0_Cause &= ~(1 << CP0Ca_BD);
}
env->CP0_Status |= (1 << CP0St_EXL);
- env->hflags |= MIPS_HFLAG_64;
+ env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
env->hflags &= ~MIPS_HFLAG_UM;
- env->hflags |= MIPS_HFLAG_CP0;
}
env->hflags &= ~MIPS_HFLAG_BMASK;
if (env->CP0_Status & (1 << CP0St_BEV)) {
val = T0 & mask;
old = env->CP0_Status;
- if (!(val & (1 << CP0St_EXL)) &&
- !(val & (1 << CP0St_ERL)) &&
- !(env->hflags & MIPS_HFLAG_DM) &&
- (val & (1 << CP0St_UM)))
- env->hflags |= MIPS_HFLAG_UM;
-#ifdef TARGET_MIPS64
- if ((env->hflags & MIPS_HFLAG_UM) &&
- !(val & (1 << CP0St_PX)) &&
- !(val & (1 << CP0St_UX)))
- env->hflags &= ~MIPS_HFLAG_64;
-#endif
- if ((val & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_UM))
- env->hflags |= MIPS_HFLAG_CP0;
- else
- env->hflags &= ~MIPS_HFLAG_CP0;
- if (val & (1 << CP0St_CU1))
- env->hflags |= MIPS_HFLAG_FPU;
- else
- env->hflags &= ~MIPS_HFLAG_FPU;
- if (val & (1 << CP0St_FR))
- env->hflags |= MIPS_HFLAG_F64;
- else
- env->hflags &= ~MIPS_HFLAG_F64;
env->CP0_Status = (env->CP0_Status & ~mask) | val;
+ CALL_FROM_TB1(compute_hflags, env);
if (loglevel & CPU_LOG_EXEC)
CALL_FROM_TB2(do_mtc0_status_debug, old, val);
CALL_FROM_TB1(cpu_mips_update_irq, env);
env->PC[env->current_tc] = env->CP0_EPC;
env->CP0_Status &= ~(1 << CP0St_EXL);
}
- if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
- !(env->CP0_Status & (1 << CP0St_ERL)) &&
- !(env->hflags & MIPS_HFLAG_DM) &&
- (env->CP0_Status & (1 << CP0St_UM)))
- env->hflags |= MIPS_HFLAG_UM;
-#ifdef TARGET_MIPS64
- if ((env->hflags & MIPS_HFLAG_UM) &&
- !(env->CP0_Status & (1 << CP0St_PX)) &&
- !(env->CP0_Status & (1 << CP0St_UX)))
- env->hflags &= ~MIPS_HFLAG_64;
-#endif
- if ((env->CP0_Status & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_UM))
- env->hflags |= MIPS_HFLAG_CP0;
- else
- env->hflags &= ~MIPS_HFLAG_CP0;
+ CALL_FROM_TB1(compute_hflags, env);
if (loglevel & CPU_LOG_EXEC)
CALL_FROM_TB0(debug_post_eret);
env->CP0_LLAddr = 1;
if (loglevel & CPU_LOG_EXEC)
CALL_FROM_TB0(debug_pre_eret);
env->PC[env->current_tc] = env->CP0_DEPC;
- env->hflags |= MIPS_HFLAG_DM;
- if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
- !(env->CP0_Status & (1 << CP0St_ERL)) &&
- !(env->hflags & MIPS_HFLAG_DM) &&
- (env->CP0_Status & (1 << CP0St_UM)))
- env->hflags |= MIPS_HFLAG_UM;
-#ifdef TARGET_MIPS64
- if ((env->hflags & MIPS_HFLAG_UM) &&
- !(env->CP0_Status & (1 << CP0St_PX)) &&
- !(env->CP0_Status & (1 << CP0St_UX)))
- env->hflags &= ~MIPS_HFLAG_64;
-#endif
- if ((env->CP0_Status & (1 << CP0St_CU0)) || !(env->hflags & MIPS_HFLAG_UM))
- env->hflags |= MIPS_HFLAG_CP0;
- else
- env->hflags &= ~MIPS_HFLAG_CP0;
+ env->hflags &= MIPS_HFLAG_DM;
+ CALL_FROM_TB1(compute_hflags, env);
if (loglevel & CPU_LOG_EXEC)
CALL_FROM_TB0(debug_post_eret);
env->CP0_LLAddr = 1;