ppc/pnv: change core mask for POWER9

When addressed by XSCOM, the first core has the 0x20 chiplet ID but
the CPU PIR can start at 0x0.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 536162b2747c3200f9ec3b39346bb301fd333c5c..f9591cd41d36b4b61de50092cc7ba890706b5cea 100644 (file)
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -707,9 +707,9 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
 #define POWER8_CORE_MASK   (0x7e7eull)
 
 /*
- * POWER9 has 24 cores, ids starting at 0x20
+ * POWER9 has 24 cores, ids starting at 0x0
  */
-#define POWER9_CORE_MASK   (0xffffff00000000ull)
+#define POWER9_CORE_MASK   (0xffffffffffffffull)
 
 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
 {

diff --git a/tests/pnv-xscom-test.c b/tests/pnv-xscom-test.c
index a1a119c0912cfad43a55dda83eb15763fa1f7ff9..9d545c4718135656c6138e610a5e82219e0176b9 100644 (file)
--- a/tests/pnv-xscom-test.c
+++ b/tests/pnv-xscom-test.c
@@ -49,7 +49,7 @@ static const PnvChip pnv_chips[] = {
         .xscom_base = 0x000603fc00000000ull,
         .xscom_core_base = 0x0ull,
         .cfam_id    = 0x220d104900008000ull,
-        .first_core = 0x20,
+        .first_core = 0x0,
     },
 #endif
 };