struct qmp_phy_cfg {
/* phy-type - PCIE/UFS/USB */
unsigned int type;
- /* number of lanes provided by phy */
- int nlanes;
+ int lanes;
/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
const struct qmp_phy_init_tbl *serdes_tbl;
/* true, if PHY has a separate DP_COM control block */
bool has_phy_dp_com_ctrl;
- /* true, if PHY has secondary tx/rx lanes to be configured */
- bool is_dual_lane_phy;
/* Offset from PCS to PCS_USB region */
unsigned int pcs_usb_offset;
static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
.type = PHY_TYPE_USB3,
- .nlanes = 1,
+ .lanes = 2,
.serdes_tbl = qmp_v3_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
.has_phy_dp_com_ctrl = true,
- .is_dual_lane_phy = true,
};
static const struct qmp_phy_cfg sc7180_dpphy_cfg = {
.type = PHY_TYPE_DP,
- .nlanes = 1,
+ .lanes = 2,
.serdes_tbl = qmp_v3_dp_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
.regs = qmp_v3_usb3phy_regs_layout,
.has_phy_dp_com_ctrl = true,
- .is_dual_lane_phy = true,
.dp_aux_init = qcom_qmp_v3_phy_dp_aux_init,
.configure_dp_tx = qcom_qmp_v3_phy_configure_dp_tx,
static const struct qmp_phy_cfg sdm845_usb3phy_cfg = {
.type = PHY_TYPE_USB3,
- .nlanes = 1,
+ .lanes = 2,
.serdes_tbl = qmp_v3_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
.has_phy_dp_com_ctrl = true,
- .is_dual_lane_phy = true,
};
static const struct qmp_phy_combo_cfg sdm845_usb3dpphy_cfg = {
static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
.type = PHY_TYPE_USB3,
- .nlanes = 1,
+ .lanes = 2,
.serdes_tbl = sm8150_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
.has_phy_dp_com_ctrl = true,
- .is_dual_lane_phy = true,
};
static const struct qmp_phy_cfg sc8180x_dpphy_cfg = {
.type = PHY_TYPE_DP,
- .nlanes = 1,
+ .lanes = 2,
.serdes_tbl = qmp_v4_dp_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
.regs = qmp_v3_usb3phy_regs_layout,
.has_phy_dp_com_ctrl = true,
- .is_dual_lane_phy = true,
.dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
.configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
static const struct qmp_phy_cfg sc8280xp_usb43dp_usb_cfg = {
.type = PHY_TYPE_USB3,
- .nlanes = 1,
+ .lanes = 2,
.serdes_tbl = sc8280xp_usb43dp_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl),
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
.has_phy_dp_com_ctrl = true,
- .is_dual_lane_phy = true,
};
static const struct qmp_phy_cfg sc8280xp_usb43dp_dp_cfg = {
.type = PHY_TYPE_DP,
- .nlanes = 1,
+ .lanes = 2,
.serdes_tbl = qmp_v5_dp_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl),
.regs = qmp_v4_usb3phy_regs_layout,
.has_phy_dp_com_ctrl = true,
- .is_dual_lane_phy = true,
.dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
.configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
.type = PHY_TYPE_USB3,
- .nlanes = 1,
+ .lanes = 2,
.serdes_tbl = sm8150_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
.pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
.has_phy_dp_com_ctrl = true,
- .is_dual_lane_phy = true,
};
static const struct qmp_phy_cfg sm8250_dpphy_cfg = {
.type = PHY_TYPE_DP,
- .nlanes = 1,
+ .lanes = 2,
.serdes_tbl = qmp_v4_dp_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
.regs = qmp_v4_usb3phy_regs_layout,
.has_phy_dp_com_ctrl = true,
- .is_dual_lane_phy = true,
.dp_aux_init = qcom_qmp_v4_phy_dp_aux_init,
.configure_dp_tx = qcom_qmp_v4_phy_configure_dp_tx,
/* Tx, Rx, and PCS configurations */
qmp_combo_configure_lane(tx, cfg->regs, cfg->tx_tbl, cfg->tx_tbl_num, 1);
- if (cfg->is_dual_lane_phy) {
+ if (cfg->lanes >= 2) {
qmp_combo_configure_lane(qphy->tx2, cfg->regs, cfg->tx_tbl,
cfg->tx_tbl_num, 2);
}
qmp_combo_configure_lane(rx, cfg->regs, cfg->rx_tbl, cfg->rx_tbl_num, 1);
- if (cfg->is_dual_lane_phy) {
+ if (cfg->lanes >= 2) {
qmp_combo_configure_lane(qphy->rx2, cfg->regs, cfg->rx_tbl,
cfg->rx_tbl_num, 2);
}
if (cfg->pcs_usb_offset)
qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset;
- if (cfg->is_dual_lane_phy) {
+ if (cfg->lanes >= 2) {
qphy->tx2 = devm_of_iomap(dev, np, 3, NULL);
if (IS_ERR(qphy->tx2))
return PTR_ERR(qphy->tx2);