arm64: tegra: Fixup SYSRAM references
authorThierry Reding <treding@nvidia.com>
Fri, 12 Nov 2021 12:35:37 +0000 (13:35 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 17 Aug 2022 12:23:12 +0000 (14:23 +0200)
[ Upstream commit 7fa307524a4d721d4a04523018509882c5414e72 ]

The json-schema bindings for SRAM expect the nodes to be called "sram"
rather than "sysram" or "shmem". Furthermore, place the brackets around
the SYSRAM references such that a two-element array is created rather
than a two-element array nested in a single-element array. This is not
relevant for device tree itself, but allows the nodes to be properly
validated against json-schema bindings.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/arm64/boot/dts/nvidia/tegra186.dtsi
arch/arm64/boot/dts/nvidia/tegra194.dtsi
arch/arm64/boot/dts/nvidia/tegra234.dtsi

index 062e87e893316bbe33a81a201e5147a51b5e4582..8354512d7b1c6d0408e935ac7172190d581b2589 100644 (file)
                iommus = <&smmu TEGRA186_SID_BPMP>;
                mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
                                    TEGRA_HSP_DB_MASTER_BPMP>;
-               shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
+               shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
                #clock-cells = <1>;
                #reset-cells = <1>;
                #power-domain-cells = <1>;
index 510d2974470cd68096ba09d8e01091b5aef8b00a..a56fb83839a49830d70e28065d97db359be0b3c3 100644 (file)
                compatible = "nvidia,tegra186-bpmp";
                mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
                                    TEGRA_HSP_DB_MASTER_BPMP>;
-               shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
+               shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
                #clock-cells = <1>;
                #reset-cells = <1>;
                #power-domain-cells = <1>;
index f0efb3a62804080366ee4f26bb875adeeb848407..28961ed31d87f27ba2db8e33b815515f3a6698aa 100644 (file)
                };
        };
 
-       sysram@40000000 {
+       sram@40000000 {
                compatible = "nvidia,tegra234-sysram", "mmio-sram";
                reg = <0x0 0x40000000 0x0 0x50000>;
                #address-cells = <1>;
                #size-cells = <1>;
                ranges = <0x0 0x0 0x40000000 0x50000>;
 
-               cpu_bpmp_tx: shmem@4e000 {
+               cpu_bpmp_tx: sram@4e000 {
                        reg = <0x4e000 0x1000>;
                        label = "cpu-bpmp-tx";
                        pool;
                };
 
-               cpu_bpmp_rx: shmem@4f000 {
+               cpu_bpmp_rx: sram@4f000 {
                        reg = <0x4f000 0x1000>;
                        label = "cpu-bpmp-rx";
                        pool;
                compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
                mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
                                    TEGRA_HSP_DB_MASTER_BPMP>;
-               shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
+               shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
                #clock-cells = <1>;
                #reset-cells = <1>;
                #power-domain-cells = <1>;