clk: renesas: r8a779f0: Add SASYNCPER internal clock

Add the SASYNCPER internal clock, which is the clock source of the
various SASYNCPERD[124] clocks, to match the clock tree diagram in the
documentation.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reported-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/18e6765bfc3bf7c3ee5ce93a370d377c1d17728e.1665558014.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index 8e7b9180ec67bbf608b32c30d1ccc10216bdec1e..e4f2bbbfeb2d2ae4df39350b43f89945206ebe9e 100644 (file)
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -42,6 +42,7 @@ enum clk_ids {
        CLK_PLL5_DIV4,
        CLK_PLL6_DIV2,
        CLK_S0,
+       CLK_SASYNCPER,
        CLK_SDSRC,
        CLK_RPCSRC,
        CLK_OCO,
@@ -71,6 +72,7 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
        DEF_FIXED(".pll6_div2", CLK_PLL6_DIV2,  CLK_PLL6,       2, 1),
        DEF_FIXED(".s0",        CLK_S0,         CLK_PLL1_DIV2,  2, 1),
 
+       DEF_FIXED(".sasyncper", CLK_SASYNCPER,  CLK_PLL5_DIV4,  3, 1),
        DEF_BASE(".sdsrc",      CLK_SDSRC,      CLK_TYPE_GEN4_SDSRC, CLK_PLL5),
        DEF_RATE(".oco",        CLK_OCO,        32768),
 
@@ -109,9 +111,9 @@ static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
        DEF_FIXED("cpex",       R8A779F0_CLK_CPEX,      CLK_EXTAL,      2, 1),
 
        DEF_FIXED("sasyncrt",   R8A779F0_CLK_SASYNCRT,  CLK_PLL5_DIV4,  48, 1),
-       DEF_FIXED("sasyncperd1", R8A779F0_CLK_SASYNCPERD1, CLK_PLL5_DIV4, 3, 1),
-       DEF_FIXED("sasyncperd2", R8A779F0_CLK_SASYNCPERD2, R8A779F0_CLK_SASYNCPERD1, 2, 1),
-       DEF_FIXED("sasyncperd4", R8A779F0_CLK_SASYNCPERD4, R8A779F0_CLK_SASYNCPERD1, 4, 1),
+       DEF_FIXED("sasyncperd1",R8A779F0_CLK_SASYNCPERD1, CLK_SASYNCPER,1, 1),
+       DEF_FIXED("sasyncperd2",R8A779F0_CLK_SASYNCPERD2, CLK_SASYNCPER,2, 1),
+       DEF_FIXED("sasyncperd4",R8A779F0_CLK_SASYNCPERD4, CLK_SASYNCPER,4, 1),
 
        DEF_GEN4_SDH("sd0h",    R8A779F0_CLK_SD0H,      CLK_SDSRC,         0x870),
        DEF_GEN4_SD("sd0",      R8A779F0_CLK_SD0,       R8A779F0_CLK_SD0H, 0x870),