arm64: dts: imx8mm-beacon: Align pin configuration group names with schema

Device tree schema expects pin configuration groups to end with 'grp'
suffix.  This fixes dtbs_check warnings like:

  pinctrl@30330000: 'pcal6414-gpio', 'pmicirq', 'usdhc1grp100mhz', 'usdhc1grp200mhz', 'usdhc1grpgpio',
    'usdhc2grp100mhz', 'usdhc2grp200mhz', 'usdhc2grpgpio', 'usdhc3grp100mhz', 'usdhc3grp200mhz'
    do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
index 5b5af8b381df0635f2edcba065405bcb5bf67338..d6b9dedd168f1f80ae4b83df64bede36a038f8e5 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
@@ -210,7 +210,7 @@
                >;
        };
 
-       pinctrl_pcal6414: pcal6414-gpio {
+       pinctrl_pcal6414: pcal6414-gpiogrp {
                fsl,pins = <
                        MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27               0x19
                >;
@@ -240,7 +240,7 @@
                >;
        };
 
-       pinctrl_usdhc2_gpio: usdhc2grpgpio {
+       pinctrl_usdhc2_gpio: usdhc2gpiogrp {
                fsl,pins = <
                        MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B       0x41
                        MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
@@ -259,7 +259,7 @@
                >;
        };
 
-       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+       pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
                fsl,pins = <
                        MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
                        MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
@@ -271,7 +271,7 @@
                >;
        };
 
-       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+       pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
                fsl,pins = <
                        MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
                        MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
index 620a124dfb5fb18f3320a0c1690a8fd7bdb6f01a..502faf6144b0a53697d2b7f50e998f782e38b186 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
@@ -290,7 +290,7 @@
                        >;
                };
 
-               pinctrl_pmic: pmicirq {
+               pinctrl_pmic: pmicirqgrp {
                        fsl,pins = <
                                MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x41
                        >;
@@ -309,7 +309,7 @@
                        >;
                };
 
-               pinctrl_usdhc1_gpio: usdhc1grpgpio {
+               pinctrl_usdhc1_gpio: usdhc1gpiogrp {
                        fsl,pins = <
                                MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10     0x41
                        >;
@@ -326,7 +326,7 @@
                        >;
                };
 
-               pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+               pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
                        fsl,pins = <
                                MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
                                MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
@@ -337,7 +337,7 @@
                        >;
                };
 
-               pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+               pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
                        fsl,pins = <
                                MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
                                MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
@@ -364,7 +364,7 @@
                        >;
                };
 
-               pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+               pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
                        fsl,pins = <
                                MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
                                MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
@@ -380,7 +380,7 @@
                        >;
                };
 
-               pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+               pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
                        fsl,pins = <
                                MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
                                MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6