drm/xe/xe2: Add workaround 16020292621

Workaround applies to Graphics 20.04 as part of ring
submission

V4(MattR):
  - Rule for engine in oob WA not supported, add explicitly
V3(MattR):
  - Pass hwe and rename API name to hint end of ring work
  - Use existing RING_NOPID API
V2:
  - Marking this WA for 20.04 instead of 20.00

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
index 4402f72481dcde677f837812c8b1a1fd72f6c680..f1c5bf203b3dc990b7d9028534d591133c1339bb 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
+++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
@@ -48,6 +48,7 @@
 #define   PIPE_CONTROL_TILE_CACHE_FLUSH                        (1<<28)
 #define   PIPE_CONTROL_AMFS_FLUSH                      (1<<25)
 #define   PIPE_CONTROL_GLOBAL_GTT_IVB                  (1<<24)
+#define   PIPE_CONTROL_LRI_POST_SYNC                   BIT(23)
 #define   PIPE_CONTROL_STORE_DATA_INDEX                        (1<<21)
 #define   PIPE_CONTROL_CS_STALL                                (1<<20)
 #define   PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET           (1<<19)

diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 59e0aa2d6a4c5214165aec3a476af11db21f21b6..1201e42ef823c6cfa4964fe8f2000d6a1eae6a1a 100644 (file)
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -7,6 +7,7 @@
 
 #include "generated/xe_wa_oob.h"
 #include "instructions/xe_mi_commands.h"
+#include "regs/xe_engine_regs.h"
 #include "regs/xe_gpu_commands.h"
 #include "regs/xe_gt_regs.h"
 #include "regs/xe_lrc_layout.h"
@@ -184,6 +185,23 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
        return i;
 }
 
+static int emit_pipe_control_to_ring_end(struct xe_hw_engine *hwe, u32 *dw, int i)
+{
+       if (hwe->class != XE_ENGINE_CLASS_RENDER)
+               return i;
+
+       if (XE_WA(hwe->gt, 16020292621)) {
+               dw[i++] = GFX_OP_PIPE_CONTROL(6);
+               dw[i++] = PIPE_CONTROL_LRI_POST_SYNC;
+               dw[i++] = RING_NOPID(hwe->mmio_base).addr;
+               dw[i++] = 0;
+               dw[i++] = 0;
+               dw[i++] = 0;
+       }
+
+       return i;
+}
+
 static int emit_pipe_imm_ggtt(u32 addr, u32 value, bool stall_only, u32 *dw,
                              int i)
 {
@@ -342,6 +360,8 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job,
 
        i = emit_user_interrupt(dw, i);
 
+       i = emit_pipe_control_to_ring_end(job->q->hwe, dw, i);
+
        xe_gt_assert(gt, i <= MAX_JOB_SIZE_DW);
 
        xe_lrc_write_ring(lrc, dw, i * sizeof(*dw));

diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index c7b7d40b5d5757fb32a5b90ae1caa04946d08974..727bdc42921249a342e279b34156cd235535db82 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -21,3 +21,4 @@
 22010954014    PLATFORM(DG2)
 14019821291    MEDIA_VERSION_RANGE(1300, 2000)
 14015076503    MEDIA_VERSION(1300)
+16020292621    GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0)