#define  ESDHC_MIX_CTRL_AC23EN         (1 << 7)
 #define  ESDHC_MIX_CTRL_EXE_TUNE       (1 << 22)
 #define  ESDHC_MIX_CTRL_SMPCLK_SEL     (1 << 23)
+#define  ESDHC_MIX_CTRL_AUTO_TUNE_EN   (1 << 24)
 #define  ESDHC_MIX_CTRL_FBCLK_SEL      (1 << 25)
 #define  ESDHC_MIX_CTRL_HS400_EN       (1 << 26)
 /* Bits 3 and 6 are not SDHCI standard definitions */
                        } else {
                                v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
                                m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
+                               m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN;
                        }
 
                        if (val & SDHCI_CTRL_EXEC_TUNING) {
                                v |= ESDHC_MIX_CTRL_EXE_TUNE;
                                m |= ESDHC_MIX_CTRL_FBCLK_SEL;
+                               m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN;
                                tuning_ctrl = readl(host->ioaddr + ESDHC_TUNING_CTRL);
                                tuning_ctrl |= ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP_DEFAULT;
                                if (imx_data->boarddata.tuning_start_tap) {