clk: at91: sama7g5: set low limit for mck0 at 32KHz

MCK0 could go as low as 32KHz. Set this limit.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20211011112719.3951784-15-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index fd9d17eabf549fc2f18dd9e12db08a1d7ed53b9e..369dfafabbca267cd38a501a2190b342355f3ff7 100644 (file)
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -850,7 +850,7 @@ static const struct {
 
 /* MCK0 characteristics. */
 static const struct clk_master_characteristics mck0_characteristics = {
-       .output = { .min = 50000000, .max = 200000000 },
+       .output = { .min = 32768, .max = 200000000 },
        .divisors = { 1, 2, 4, 3, 5 },
        .have_div3_pres = 1,
 };