amdgpu_ring_write(ring, 1 << vmid);
 }
 
+static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
+                                       uint32_t reg, uint32_t val)
+{
+       amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
+       amdgpu_ring_write(ring, reg << 2);
+       amdgpu_ring_write(ring, val);
+}
+
 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
                                        struct amdgpu_irq_src *source,
                                        unsigned type,
        .pad_ib = amdgpu_ring_generic_pad_ib,
        .begin_use = amdgpu_vcn_ring_begin_use,
        .end_use = amdgpu_vcn_ring_end_use,
+       .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
 };
 
 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {