RISC-V: KVM: Allow Guest use Zihintpause extension
authorMayuresh Chitale <mchitale@ventanamicro.com>
Sun, 2 Oct 2022 04:48:48 +0000 (10:18 +0530)
committerAnup Patel <anup@brainfault.org>
Sun, 2 Oct 2022 04:48:48 +0000 (10:18 +0530)
We should advertise Zihintpause ISA extension to KVM user-space whenever
host supports it. This will allow KVM user-space (i.e. QEMU or KVMTOOL)
to pass on this information to Guest via ISA string.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/uapi/asm/kvm.h
arch/riscv/kvm/vcpu.c

index b6770ee0887211ec1323744f6778ea13bcda66b2..9085b90cf3247f38ed1bb0818092cbd97bbc57c5 100644 (file)
@@ -99,6 +99,7 @@ enum KVM_RISCV_ISA_EXT_ID {
        KVM_RISCV_ISA_EXT_SVPBMT,
        KVM_RISCV_ISA_EXT_SSTC,
        KVM_RISCV_ISA_EXT_SVINVAL,
+       KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
        KVM_RISCV_ISA_EXT_MAX,
 };
 
index 901bb5c0cb50396b8552be46695930df83a0c817..0de0dd22e734cc5d5fd845cd87c9b4540168c1c7 100644 (file)
@@ -54,6 +54,7 @@ static const unsigned long kvm_isa_ext_arr[] = {
        RISCV_ISA_EXT_SVPBMT,
        RISCV_ISA_EXT_SSTC,
        RISCV_ISA_EXT_SVINVAL,
+       RISCV_ISA_EXT_ZIHINTPAUSE,
 };
 
 static unsigned long kvm_riscv_vcpu_base2isa_ext(unsigned long base_ext)
@@ -89,6 +90,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext)
        case KVM_RISCV_ISA_EXT_M:
        case KVM_RISCV_ISA_EXT_SSTC:
        case KVM_RISCV_ISA_EXT_SVINVAL:
+       case KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
                return false;
        default:
                break;