arm64: dts: qcom: sc7280: Use WPSS PAS instead of PIL

The wpss-pil driver wants to manage too many resources that cannot be
touched with standard Qualcomm firmware.

Use the compatible from the PAS driver and move the ChromeOS-specific
bits to sc7280-chrome-common.dtsi.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20231208-sc7280-remoteprocs-v3-7-6aa394d33edf@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
index 88fc67c3646e5cd9fc479500fc139b4f5254812d..9845638b344a32e362779eabfcec205123e78895 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
@@ -97,8 +97,25 @@
 };
 
 &remoteproc_wpss {
-       status = "okay";
+       compatible = "qcom,sc7280-wpss-pil";
+       clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
+                <&gcc GCC_WPSS_AHB_CLK>,
+                <&gcc GCC_WPSS_RSCP_CLK>,
+                <&rpmhcc RPMH_CXO_CLK>;
+       clock-names = "ahb_bdg",
+                     "ahb",
+                     "rscp",
+                     "xo";
+
+       resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
+                <&pdc_reset PDC_WPSS_SYNC_RESET>;
+       reset-names = "restart", "pdc_sync";
+
+       qcom,halt-regs = <&tcsr_1 0x17000>;
+
        firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
+
+       status = "okay";
 };
 
 &scm {

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index f5e5cc046954bb2d98397996379a99e868da33c1..132b55e64579126dda7f05599e86546f3f67c2b3 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3594,7 +3594,7 @@
                };
 
                remoteproc_wpss: remoteproc@8a00000 {
-                       compatible = "qcom,sc7280-wpss-pil";
+                       compatible = "qcom,sc7280-wpss-pas";
                        reg = <0 0x08a00000 0 0x10000>;
 
                        interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
@@ -3606,12 +3606,8 @@
                        interrupt-names = "wdog", "fatal", "ready", "handover",
                                          "stop-ack", "shutdown-ack";
 
-                       clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
-                                <&gcc GCC_WPSS_AHB_CLK>,
-                                <&gcc GCC_WPSS_RSCP_CLK>,
-                                <&rpmhcc RPMH_CXO_CLK>;
-                       clock-names = "ahb_bdg", "ahb",
-                                     "rscp", "xo";
+                       clocks = <&rpmhcc RPMH_CXO_CLK>;
+                       clock-names = "xo";
 
                        power-domains = <&rpmhpd SC7280_CX>,
                                        <&rpmhpd SC7280_MX>;
@@ -3624,11 +3620,6 @@
                        qcom,smem-states = <&wpss_smp2p_out 0>;
                        qcom,smem-state-names = "stop";
 
-                       resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
-                                <&pdc_reset PDC_WPSS_SYNC_RESET>;
-                       reset-names = "restart", "pdc_sync";
-
-                       qcom,halt-regs = <&tcsr_1 0x17000>;
 
                        status = "disabled";