return ret;
 
                ret = regmap_read(t_map, SDIF_DATA(channel), &nbs);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                nbs &= SAMPLE_DATA_MSK;
                        return ret;
 
                ret = regmap_read(v_map, VM_SDIF_DATA(vm_idx, ch_idx), &n);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                n &= SAMPLE_DATA_MSK;
 
        if (t_num) {
                ret = regmap_write(t_map, SDIF_SMPL_CTRL, 0x0);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_write(t_map, SDIF_HALT, 0x0);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_write(t_map, CLK_SYNTH, clk_synth);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_write(t_map, SDIF_DISABLE, 0x0);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
                val = CFG0_MODE_2 | CFG0_PARALLEL_OUT | CFG0_12_BIT |
                      IP_CFG << SDIF_ADDR_SFT | SDIF_WRN_W | SDIF_PROG;
                ret = regmap_write(t_map, SDIF_W, val);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
                val = POWER_DELAY_CYCLE_256 | IP_TMR << SDIF_ADDR_SFT |
                              SDIF_WRN_W | SDIF_PROG;
                ret = regmap_write(t_map, SDIF_W, val);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_read_poll_timeout(t_map, SDIF_STAT,
                      IP_CTRL << SDIF_ADDR_SFT |
                      SDIF_WRN_W | SDIF_PROG;
                ret = regmap_write(t_map, SDIF_W, val);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
        }
 
        if (p_num) {
                ret = regmap_write(p_map, SDIF_HALT, 0x0);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_write(p_map, SDIF_DISABLE, BIT(p_num) - 1);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_write(p_map, CLK_SYNTH, clk_synth);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
        }
 
        if (v_num) {
                ret = regmap_write(v_map, SDIF_SMPL_CTRL, 0x0);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_write(v_map, SDIF_HALT, 0x0);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_write(v_map, CLK_SYNTH, clk_synth);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_write(v_map, SDIF_DISABLE, 0x0);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
                      CFG1_14_BIT | IP_CFG << SDIF_ADDR_SFT |
                      SDIF_WRN_W | SDIF_PROG;
                ret = regmap_write(v_map, SDIF_W, val);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
                val = POWER_DELAY_CYCLE_64 | IP_TMR << SDIF_ADDR_SFT |
                      SDIF_WRN_W | SDIF_PROG;
                ret = regmap_write(v_map, SDIF_W, val);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
 
                ret = regmap_read_poll_timeout(v_map, SDIF_STAT,
                      IP_CTRL << SDIF_ADDR_SFT |
                      SDIF_WRN_W | SDIF_PROG;
                ret = regmap_write(v_map, SDIF_W, val);
-               if(ret < 0)
+               if (ret < 0)
                        return ret;
        }
 
        }
 
        ret = regmap_read(pvt->c_map, PVT_IP_CONFIG, &val);
-       if(ret < 0)
+       if (ret < 0)
                return ret;
 
        ts_num = (val & TS_NUM_MSK) >> TS_NUM_SFT;