arm64/sme: Automatically generate defines for SMCR

Convert SMCR to use the register definition code, no functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20220510161208.631259-8-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index a2f0759f65b2706d5ba41e0c5fe7df024a60ece8..cbf03a1f316e49f61ea58beb4dded577819ac013 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -216,7 +216,6 @@
 #define SYS_ZCR_EL1                    sys_reg(3, 0, 1, 2, 0)
 #define SYS_TRFCR_EL1                  sys_reg(3, 0, 1, 2, 1)
 #define SYS_SMPRI_EL1                  sys_reg(3, 0, 1, 2, 4)
-#define SYS_SMCR_EL1                   sys_reg(3, 0, 1, 2, 6)
 
 #define SYS_TCR_EL1                    sys_reg(3, 0, 2, 0, 2)
 
@@ -571,7 +570,6 @@
 #define SYS_TRFCR_EL2                  sys_reg(3, 4, 1, 2, 1)
 #define SYS_HCRX_EL2                   sys_reg(3, 4, 1, 2, 2)
 #define SYS_SMPRIMAP_EL2               sys_reg(3, 4, 1, 2, 5)
-#define SYS_SMCR_EL2                   sys_reg(3, 4, 1, 2, 6)
 #define SYS_DACR32_EL2                 sys_reg(3, 4, 3, 0, 0)
 #define SYS_HDFGRTR_EL2                        sys_reg(3, 4, 3, 1, 4)
 #define SYS_HDFGWTR_EL2                        sys_reg(3, 4, 3, 1, 5)
@@ -631,7 +629,6 @@
 #define SYS_SCTLR_EL12                 sys_reg(3, 5, 1, 0, 0)
 #define SYS_CPACR_EL12                 sys_reg(3, 5, 1, 0, 2)
 #define SYS_ZCR_EL12                   sys_reg(3, 5, 1, 2, 0)
-#define SYS_SMCR_EL12                  sys_reg(3, 5, 1, 2, 6)
 #define SYS_TTBR0_EL12                 sys_reg(3, 5, 2, 0, 0)
 #define SYS_TTBR1_EL12                 sys_reg(3, 5, 2, 0, 1)
 #define SYS_TCR_EL12                   sys_reg(3, 5, 2, 0, 2)
@@ -1117,13 +1114,6 @@
 #define ZCR_ELx_LEN_WIDTH      4
 #define ZCR_ELx_LEN_MASK       0xf
 
-#define SMCR_ELx_FA64_SHIFT    31
-#define SMCR_ELx_FA64_MASK     (1 << SMCR_ELx_FA64_SHIFT)
-
-#define SMCR_ELx_LEN_SHIFT     0
-#define SMCR_ELx_LEN_WIDTH     4
-#define SMCR_ELx_LEN_MASK      0xf
-
 #define CPACR_EL1_FPEN_EL1EN   (BIT(20)) /* enable EL1 access */
 #define CPACR_EL1_FPEN_EL0EN   (BIT(21)) /* enable EL0 access, if EL1EN set */
 

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index c5619629bf9c0ba844e6c8170a040605838d8191..d0ac576480007d08a1ce4ab33889731c1bcd8976 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -185,6 +185,26 @@ Field      1       A
 Field  0       M
 EndSysreg
 
+SysregFields   SMCR_ELx
+Res0   63:32
+Field  31      FA64
+Res0   30:9
+Raz    8:4
+Field  3:0     LEN
+EndSysregFields
+
+Sysreg SMCR_EL1        3       0       1       2       6
+Fields SMCR_ELx
+EndSysreg
+
+Sysreg SMCR_EL2        3       4       1       2       6
+Fields SMCR_ELx
+EndSysreg
+
+Sysreg SMCR_EL12       3       5       1       2       6
+Fields SMCR_ELx
+EndSysreg
+
 SysregFields TTBRx_EL1
 Field  63:48   ASID
 Field  47:1    BADDR