drm/amd/display: Add minimum Z8 residency debug option

[Why]
Allows finer control and tuning for debug and profiling.

[How]
Add the debug option into DC. The default remains the same as before
for now.

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index c3814f40a102b33bc7dbc0831dcd5e4023654c5f..f1ea9031a191a7ef354d02db875f2683813f7386 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -795,6 +795,7 @@ struct dc_debug_options {
        unsigned int force_odm_combine; //bit vector based on otg inst
        unsigned int seamless_boot_odm_combine;
        unsigned int force_odm_combine_4to1; //bit vector based on otg inst
+       int minimum_z8_residency_time;
        bool disable_z9_mpc;
        unsigned int force_fclk_khz;
        bool enable_tri_buf;

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 54ed3de869d3b001d98d8f8c0ab972fe7d819065..8fc89aeb86d446309922f985115276d3d33feba6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -887,6 +887,7 @@ static const struct dc_plane_cap plane_cap = {
 static const struct dc_debug_options debug_defaults_drv = {
        .disable_z10 = false,
        .enable_z9_disable_interface = true,
+       .minimum_z8_residency_time = 1000,
        .psr_skip_crtc_disable = true,
        .disable_dmcu = true,
        .force_abm_enable = false,

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index d3ba65efe1d2e986ba7c92d81bcd1d3e318a076b..f3cfc144e35875269b23ed0c0627b44dedc7d50d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -973,7 +973,8 @@ static enum dcn_zstate_support_state  decide_zstate_support(struct dc *dc, struc
        else if (context->stream_count == 1 &&  context->streams[0]->signal == SIGNAL_TYPE_EDP) {
                struct dc_link *link = context->streams[0]->sink->link;
                struct dc_stream_status *stream_status = &context->stream_status[0];
-               bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > 1000.0;
+               int minmum_z8_residency = dc->debug.minimum_z8_residency_time > 0 ? dc->debug.minimum_z8_residency_time : 1000;
+               bool allow_z8 = context->bw_ctx.dml.vba.StutterPeriod > (double)minmum_z8_residency;
                bool is_pwrseq0 = link->link_index == 0;
 
                if (dc_extended_blank_supported(dc)) {