riscv: dts: microchip: use an mpfs specific l2 compatible
authorConor Dooley <conor.dooley@microchip.com>
Thu, 25 Aug 2022 18:04:18 +0000 (19:04 +0100)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 31 Aug 2022 15:57:51 +0000 (16:57 +0100)
PolarFire SoC does not have the same l2 cache controller as the fu540,
featuring an extra interrupt. Appease the devicetree checker overlords
by adding a PolarFire SoC specific compatible to fix the below sort of
warnings:

mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long

Fixes: 0fa6107eca41 ("RISC-V: Initial DTS for Microchip ICICLE board")
Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts")
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
arch/riscv/boot/dts/microchip/mpfs.dtsi

index 74493344ea41b440881ee6cadf9a39a9dbaa7dbc..6d9d455fa160ab12ab31582715949141c0af588f 100644 (file)
                ranges;
 
                cctrllr: cache-controller@2010000 {
-                       compatible = "sifive,fu540-c000-ccache", "cache";
+                       compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
                        reg = <0x0 0x2010000 0x0 0x1000>;
                        cache-block-size = <64>;
                        cache-level = <2>;