DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR;
                intel_uncore_rmw(&dev_priv->uncore, GEN11_CHICKEN_DCPR_2, 0, val);
        }
+
+       /* Wa_14011503030:xelpd */
+       if (DISPLAY_VER(dev_priv) >= 13)
+               intel_de_write(dev_priv, XELPD_DISPLAY_ERR_FATAL_MASK, ~0);
 }
 
 static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
 
 #define  GEN8_GT_BCS_IRQ               (1 << 1)
 #define  GEN8_GT_RCS_IRQ               (1 << 0)
 
+#define XELPD_DISPLAY_ERR_FATAL_MASK   _MMIO(0x4421c)
+
 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))