#define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
/* max 16 qps */
#define i40e_default_queues_per_vmdq(pf) \
- (test_bit(I40E_HW_RSS_AQ_CAPABLE, (pf)->hw_features) ? 4 : 1)
+ (test_bit(I40E_HW_CAP_RSS_AQ, (pf)->hw.caps) ? 4 : 1)
#define I40E_DEFAULT_QUEUES_PER_VF 4
#define I40E_MAX_VF_QUEUES 16
#define i40e_pf_get_max_q_per_tc(pf) \
- (test_bit(I40E_HW_128_QP_RSS_CAPABLE, (pf)->hw_features) ? 128 : 64)
+ (test_bit(I40E_HW_CAP_128_QP_RSS, (pf)->hw.caps) ? 128 : 64)
#define I40E_FDIR_RING_COUNT 32
#define I40E_MAX_AQ_BUF_SIZE 4096
#define I40E_AQ_LEN 256
__I40E_VSI_STATE_SIZE__,
};
-enum i40e_pf_hw_features {
- I40E_HW_RSS_AQ_CAPABLE,
- I40E_HW_128_QP_RSS_CAPABLE,
- I40E_HW_ATR_EVICT_CAPABLE,
- I40E_HW_WB_ON_ITR_CAPABLE,
- I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE,
- I40E_HW_NO_PCI_LINK_CHECK,
- I40E_HW_100M_SGMII_CAPABLE,
- I40E_HW_NO_DCB_SUPPORT,
- I40E_HW_USE_SET_LLDP_MIB,
- I40E_HW_GENEVE_OFFLOAD_CAPABLE,
- I40E_HW_PTP_L4_CAPABLE,
- I40E_HW_WOL_MC_MAGIC_PKT_WAKE,
- I40E_HW_HAVE_CRT_RETIMER,
- I40E_HW_OUTER_UDP_CSUM_CAPABLE,
- I40E_HW_PHY_CONTROLS_LEDS,
- I40E_HW_STOP_FW_LLDP,
- I40E_HW_PORT_ID_VALID,
- I40E_HW_RESTART_AUTONEG,
- I40E_PF_HW_FEATURES_NBITS, /* must be last */
-};
-
enum i40e_pf_flags {
I40E_FLAG_MSI_ENA,
I40E_FLAG_MSIX_ENA,
struct timer_list service_timer;
struct work_struct service_task;
- DECLARE_BITMAP(hw_features, I40E_PF_HW_FEATURES_NBITS);
DECLARE_BITMAP(flags, I40E_PF_FLAGS_NBITS);
struct i40e_client_instance *cinst;
bool stat_offsets_loaded;
if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
ethtool_link_ksettings_add_link_mode(ks, advertising,
1000baseT_Full);
- if (test_bit(I40E_HW_100M_SGMII_CAPABLE, pf->hw_features)) {
+ if (test_bit(I40E_HW_CAP_100M_SGMII, pf->hw.caps)) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100baseT_Full);
ethtool_link_ksettings_add_link_mode(ks, advertising,
10000baseKX4_Full);
}
if (phy_types & I40E_CAP_PHY_TYPE_10GBASE_KR &&
- !test_bit(I40E_HW_HAVE_CRT_RETIMER, pf->hw_features)) {
+ !test_bit(I40E_HW_CAP_CRT_RETIMER, pf->hw.caps)) {
ethtool_link_ksettings_add_link_mode(ks, supported,
10000baseKR_Full);
if (hw_link_info->requested_speeds & I40E_LINK_SPEED_10GB)
10000baseKR_Full);
}
if (phy_types & I40E_CAP_PHY_TYPE_1000BASE_KX &&
- !test_bit(I40E_HW_HAVE_CRT_RETIMER, pf->hw_features)) {
+ !test_bit(I40E_HW_CAP_CRT_RETIMER, pf->hw.caps)) {
ethtool_link_ksettings_add_link_mode(ks, supported,
1000baseKX_Full);
if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
if (hw_link_info->requested_speeds & I40E_LINK_SPEED_1GB)
ethtool_link_ksettings_add_link_mode(ks, advertising,
1000baseT_Full);
- if (test_bit(I40E_HW_100M_SGMII_CAPABLE, pf->hw_features)) {
+ if (test_bit(I40E_HW_CAP_100M_SGMII, pf->hw.caps)) {
ethtool_link_ksettings_add_link_mode(ks, supported,
100baseT_Full);
if (hw_link_info->requested_speeds &
BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ);
- if (test_bit(I40E_HW_PTP_L4_CAPABLE, pf->hw_features))
+ if (test_bit(I40E_HW_CAP_PTP_L4, pf->hw.caps))
info->rx_filters |= BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) |
switch (state) {
case ETHTOOL_ID_ACTIVE:
- if (!test_bit(I40E_HW_PHY_CONTROLS_LEDS, pf->hw_features)) {
+ if (!test_bit(I40E_HW_CAP_PHY_CONTROLS_LEDS, pf->hw.caps)) {
pf->led_status = i40e_led_get(hw);
} else {
if (!test_bit(I40E_HW_CAP_AQ_PHY_ACCESS, hw->caps))
}
return blink_freq;
case ETHTOOL_ID_ON:
- if (!test_bit(I40E_HW_PHY_CONTROLS_LEDS, pf->hw_features))
+ if (!test_bit(I40E_HW_CAP_PHY_CONTROLS_LEDS, pf->hw.caps))
i40e_led_set(hw, 0xf, false);
else
ret = i40e_led_set_phy(hw, true, pf->led_status, 0);
break;
case ETHTOOL_ID_OFF:
- if (!test_bit(I40E_HW_PHY_CONTROLS_LEDS, pf->hw_features))
+ if (!test_bit(I40E_HW_CAP_PHY_CONTROLS_LEDS, pf->hw.caps))
i40e_led_set(hw, 0x0, false);
else
ret = i40e_led_set_phy(hw, false, pf->led_status, 0);
break;
case ETHTOOL_ID_INACTIVE:
- if (!test_bit(I40E_HW_PHY_CONTROLS_LEDS, pf->hw_features)) {
+ if (!test_bit(I40E_HW_CAP_PHY_CONTROLS_LEDS, pf->hw.caps)) {
i40e_led_set(hw, pf->led_status, false);
} else {
ret = i40e_led_set_phy(hw, false, pf->led_status,
switch (nfc->flow_type) {
case TCP_V4_FLOW:
set_bit(I40E_FILTER_PCTYPE_NONF_IPV4_TCP, flow_pctypes);
- if (test_bit(I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE,
- pf->hw_features))
+ if (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE,
+ pf->hw.caps))
set_bit(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK,
flow_pctypes);
break;
case TCP_V6_FLOW:
set_bit(I40E_FILTER_PCTYPE_NONF_IPV6_TCP, flow_pctypes);
- if (test_bit(I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE,
- pf->hw_features))
+ if (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE,
+ pf->hw.caps))
set_bit(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK,
flow_pctypes);
break;
case UDP_V4_FLOW:
set_bit(I40E_FILTER_PCTYPE_NONF_IPV4_UDP, flow_pctypes);
- if (test_bit(I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE,
- pf->hw_features)) {
+ if (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE,
+ pf->hw.caps)) {
set_bit(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP,
flow_pctypes);
set_bit(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP,
break;
case UDP_V6_FLOW:
set_bit(I40E_FILTER_PCTYPE_NONF_IPV6_UDP, flow_pctypes);
- if (test_bit(I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE,
- pf->hw_features)) {
+ if (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE,
+ pf->hw.caps)) {
set_bit(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP,
flow_pctypes);
set_bit(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP,
/* ATR eviction is not supported on all devices */
if (test_bit(I40E_FLAG_HW_ATR_EVICT_ENA, new_flags) &&
- !test_bit(I40E_HW_ATR_EVICT_CAPABLE, pf->hw_features))
+ !test_bit(I40E_HW_CAP_ATR_EVICT, pf->hw.caps))
return -EOPNOTSUPP;
/* If the driver detected FW LLDP was disabled on init, this flag could
u8 *lut;
int ret;
- if (!test_bit(I40E_HW_RSS_AQ_CAPABLE, pf->hw_features))
+ if (!test_bit(I40E_HW_CAP_RSS_AQ, pf->hw.caps))
return 0;
if (!vsi->rss_size)
vsi->rss_size = min_t(int, pf->alloc_rss_size,
set_bit(__I40E_CLIENT_L2_CHANGE, pf->state);
}
/* registers are set, lets apply */
- if (test_bit(I40E_HW_USE_SET_LLDP_MIB, pf->hw_features))
+ if (test_bit(I40E_HW_CAP_USE_SET_LLDP_MIB, pf->hw.caps))
ret = i40e_hw_set_dcb_config(pf, new_cfg);
}
struct i40e_hw *hw = &pf->hw;
int err;
- if (test_bit(I40E_HW_USE_SET_LLDP_MIB, pf->hw_features)) {
+ if (test_bit(I40E_HW_CAP_USE_SET_LLDP_MIB, pf->hw.caps)) {
/* Update the local cached instance with TC0 ETS */
memset(&pf->tmp_cfg, 0, sizeof(struct i40e_dcbx_config));
pf->tmp_cfg.etscfg.willing = I40E_IEEE_DEFAULT_ETS_WILLING;
/* Do not enable DCB for SW1 and SW2 images even if the FW is capable
* Also do not enable DCBx if FW LLDP agent is disabled
*/
- if (test_bit(I40E_HW_NO_DCB_SUPPORT, pf->hw_features)) {
+ if (test_bit(I40E_HW_CAP_NO_DCB_SUPPORT, pf->hw.caps)) {
dev_info(&pf->pdev->dev, "DCB is not supported.\n");
err = -EOPNOTSUPP;
goto out;
wr32(hw, I40E_REG_MSS, val);
}
- if (test_bit(I40E_HW_RESTART_AUTONEG, pf->hw_features)) {
+ if (test_bit(I40E_HW_CAP_RESTART_AUTONEG, pf->hw.caps)) {
msleep(75);
ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
if (ret)
ring->count = vsi->num_tx_desc;
ring->size = 0;
ring->dcb_tc = 0;
- if (test_bit(I40E_HW_WB_ON_ITR_CAPABLE, vsi->back->hw_features))
+ if (test_bit(I40E_HW_CAP_WB_ON_ITR, vsi->back->hw.caps))
ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
ring->itr_setting = pf->tx_itr_default;
WRITE_ONCE(vsi->tx_rings[i], ring++);
ring->count = vsi->num_tx_desc;
ring->size = 0;
ring->dcb_tc = 0;
- if (test_bit(I40E_HW_WB_ON_ITR_CAPABLE, vsi->back->hw_features))
+ if (test_bit(I40E_HW_CAP_WB_ON_ITR, vsi->back->hw.caps))
ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
set_ring_xdp(ring);
ring->itr_setting = pf->tx_itr_default;
{
struct i40e_pf *pf = vsi->back;
- if (test_bit(I40E_HW_RSS_AQ_CAPABLE, pf->hw_features))
+ if (test_bit(I40E_HW_CAP_RSS_AQ, pf->hw.caps))
return i40e_config_rss_aq(vsi, seed, lut, lut_size);
else
return i40e_config_rss_reg(vsi, seed, lut, lut_size);
{
struct i40e_pf *pf = vsi->back;
- if (test_bit(I40E_HW_RSS_AQ_CAPABLE, pf->hw_features))
+ if (test_bit(I40E_HW_CAP_RSS_AQ, pf->hw.caps))
return i40e_get_rss_aq(vsi, seed, lut, lut_size);
else
return i40e_get_rss_reg(vsi, seed, lut, lut_size);
}
if (pf->hw.mac.type == I40E_MAC_X722) {
- set_bit(I40E_HW_RSS_AQ_CAPABLE, pf->hw_features);
- set_bit(I40E_HW_128_QP_RSS_CAPABLE, pf->hw_features);
- set_bit(I40E_HW_ATR_EVICT_CAPABLE, pf->hw_features);
- set_bit(I40E_HW_WB_ON_ITR_CAPABLE, pf->hw_features);
- set_bit(I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE, pf->hw_features);
- set_bit(I40E_HW_NO_PCI_LINK_CHECK, pf->hw_features);
- set_bit(I40E_HW_USE_SET_LLDP_MIB, pf->hw_features);
- set_bit(I40E_HW_GENEVE_OFFLOAD_CAPABLE, pf->hw_features);
- set_bit(I40E_HW_PTP_L4_CAPABLE, pf->hw_features);
- set_bit(I40E_HW_WOL_MC_MAGIC_PKT_WAKE, pf->hw_features);
- set_bit(I40E_HW_OUTER_UDP_CSUM_CAPABLE, pf->hw_features);
+ set_bit(I40E_HW_CAP_RSS_AQ, pf->hw.caps);
+ set_bit(I40E_HW_CAP_128_QP_RSS, pf->hw.caps);
+ set_bit(I40E_HW_CAP_ATR_EVICT, pf->hw.caps);
+ set_bit(I40E_HW_CAP_WB_ON_ITR, pf->hw.caps);
+ set_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE, pf->hw.caps);
+ set_bit(I40E_HW_CAP_NO_PCI_LINK_CHECK, pf->hw.caps);
+ set_bit(I40E_HW_CAP_USE_SET_LLDP_MIB, pf->hw.caps);
+ set_bit(I40E_HW_CAP_GENEVE_OFFLOAD, pf->hw.caps);
+ set_bit(I40E_HW_CAP_PTP_L4, pf->hw.caps);
+ set_bit(I40E_HW_CAP_WOL_MC_MAGIC_PKT_WAKE, pf->hw.caps);
+ set_bit(I40E_HW_CAP_OUTER_UDP_CSUM, pf->hw.caps);
#define I40E_FDEVICT_PCTYPE_DEFAULT 0xc03
if (rd32(&pf->hw, I40E_GLQF_FDEVICTENA(1)) !=
I40E_FDEVICT_PCTYPE_DEFAULT) {
dev_warn(&pf->pdev->dev,
"FD EVICT PCTYPES are not right, disable FD HW EVICT\n");
- clear_bit(I40E_HW_ATR_EVICT_CAPABLE, pf->hw_features);
+ clear_bit(I40E_HW_CAP_ATR_EVICT, pf->hw.caps);
}
} else if ((pf->hw.aq.api_maj_ver > 1) ||
((pf->hw.aq.api_maj_ver == 1) &&
(pf->hw.aq.api_min_ver > 4))) {
/* Supported in FW API version higher than 1.4 */
- set_bit(I40E_HW_GENEVE_OFFLOAD_CAPABLE, pf->hw_features);
+ set_bit(I40E_HW_CAP_GENEVE_OFFLOAD, pf->hw.caps);
}
/* Enable HW ATR eviction if possible */
- if (test_bit(I40E_HW_ATR_EVICT_CAPABLE, pf->hw_features))
+ if (test_bit(I40E_HW_CAP_ATR_EVICT, pf->hw.caps))
set_bit(I40E_FLAG_HW_ATR_EVICT_ENA, pf->flags);
if ((pf->hw.mac.type == I40E_MAC_XL710) &&
(((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
(pf->hw.aq.fw_maj_ver < 4))) {
- set_bit(I40E_HW_RESTART_AUTONEG, pf->hw_features);
+ set_bit(I40E_HW_CAP_RESTART_AUTONEG, pf->hw.caps);
/* No DCB support for FW < v4.33 */
- set_bit(I40E_HW_NO_DCB_SUPPORT, pf->hw_features);
+ set_bit(I40E_HW_CAP_NO_DCB_SUPPORT, pf->hw.caps);
}
/* Disable FW LLDP if FW < v4.3 */
if ((pf->hw.mac.type == I40E_MAC_XL710) &&
(((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
(pf->hw.aq.fw_maj_ver < 4)))
- set_bit(I40E_HW_STOP_FW_LLDP, pf->hw_features);
+ set_bit(I40E_HW_CAP_STOP_FW_LLDP, pf->hw.caps);
/* Use the FW Set LLDP MIB API if FW > v4.40 */
if ((pf->hw.mac.type == I40E_MAC_XL710) &&
(((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) ||
(pf->hw.aq.fw_maj_ver >= 5)))
- set_bit(I40E_HW_USE_SET_LLDP_MIB, pf->hw_features);
+ set_bit(I40E_HW_CAP_USE_SET_LLDP_MIB, pf->hw.caps);
/* Enable PTP L4 if FW > v6.0 */
if (pf->hw.mac.type == I40E_MAC_XL710 &&
pf->hw.aq.fw_maj_ver >= 6)
- set_bit(I40E_HW_PTP_L4_CAPABLE, pf->hw_features);
+ set_bit(I40E_HW_CAP_PTP_L4, pf->hw.caps);
if (pf->hw.func_caps.vmdq && num_online_cpus() != 1) {
pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
struct i40e_pf *pf = np->vsi->back;
struct i40e_hw *hw = &pf->hw;
- if (!test_bit(I40E_HW_PORT_ID_VALID, pf->hw_features))
+ if (!test_bit(I40E_HW_CAP_PORT_ID_VALID, pf->hw.caps))
return -EOPNOTSUPP;
ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
NETIF_F_RXCSUM |
0;
- if (!test_bit(I40E_HW_OUTER_UDP_CSUM_CAPABLE, pf->hw_features))
+ if (!test_bit(I40E_HW_CAP_OUTER_UDP_CSUM, pf->hw.caps))
netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
netdev->udp_tunnel_nic_info = &pf->udp_tunnel_nic;
break;
}
- if (test_bit(I40E_HW_RSS_AQ_CAPABLE, pf->hw_features) &&
+ if (test_bit(I40E_HW_CAP_RSS_AQ, pf->hw.caps) &&
vsi->type == I40E_VSI_VMDQ2) {
ret = i40e_vsi_config_rss(vsi);
if (ret)
* Ignore error return codes because if it was already disabled via
* hardware settings this will fail
*/
- if (test_bit(I40E_HW_STOP_FW_LLDP, pf->hw_features)) {
+ if (test_bit(I40E_HW_CAP_STOP_FW_LLDP, pf->hw.caps)) {
dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
i40e_aq_stop_lldp(hw, true, false, NULL);
}
ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
i40e_get_port_mac_addr(hw, hw->mac.port_addr);
if (is_valid_ether_addr(hw->mac.port_addr))
- set_bit(I40E_HW_PORT_ID_VALID, pf->hw_features);
+ set_bit(I40E_HW_CAP_PORT_ID_VALID, pf->hw.caps);
i40e_ptp_alloc_pins(pf);
pci_set_drvdata(pdev, pf);
wr32(hw, I40E_REG_MSS, val);
}
- if (test_bit(I40E_HW_RESTART_AUTONEG, pf->hw_features)) {
+ if (test_bit(I40E_HW_CAP_RESTART_AUTONEG, pf->hw.caps)) {
msleep(75);
err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
if (err)
* and will report PCI Gen 1 x 1 by default so don't bother
* checking them.
*/
- if (!test_bit(I40E_HW_NO_PCI_LINK_CHECK, pf->hw_features)) {
+ if (!test_bit(I40E_HW_CAP_NO_PCI_LINK_CHECK, pf->hw.caps)) {
char speed[PCI_SPEED_SIZE] = "Unknown";
char width[PCI_WIDTH_SIZE] = "Unknown";
if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) ||
(pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4))
- set_bit(I40E_HW_PHY_CONTROLS_LEDS, pf->hw_features);
+ set_bit(I40E_HW_CAP_PHY_CONTROLS_LEDS, pf->hw.caps);
if (pf->hw.device_id == I40E_DEV_ID_SFP_I_X722)
- set_bit(I40E_HW_HAVE_CRT_RETIMER, pf->hw_features);
+ set_bit(I40E_HW_CAP_CRT_RETIMER, pf->hw.caps);
/* print a string summarizing features */
i40e_print_features(pf);
*/
i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false);
- if (test_bit(I40E_HW_WOL_MC_MAGIC_PKT_WAKE, pf->hw_features) &&
+ if (test_bit(I40E_HW_CAP_WOL_MC_MAGIC_PKT_WAKE, pf->hw.caps) &&
pf->wol_en)
i40e_enable_mc_magic_wake(pf);
*/
i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false);
- if (test_bit(I40E_HW_WOL_MC_MAGIC_PKT_WAKE, pf->hw_features) &&
+ if (test_bit(I40E_HW_CAP_WOL_MC_MAGIC_PKT_WAKE, pf->hw.caps) &&
pf->wol_en)
i40e_enable_mc_magic_wake(pf);