scsi: ufs: qcom: Use ufshcd_rmwl() where applicable

Instead of using both ufshcd_readl() and ufshcd_writel() to read/modify/
write a register, let's make use of the existing helper.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20231208065902.11006-17-manivannan.sadhasivam@linaro.org
Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8775p-ride
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 26aa8904c823c7fee26858dbd1c888c9858e82eb..549a0864539189dfe64d56c337c62c1d1b91b5dd 100644 (file)
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -387,9 +387,8 @@ out_disable_phy:
  */
 static void ufs_qcom_enable_hw_clk_gating(struct ufs_hba *hba)
 {
-       ufshcd_writel(hba,
-               ufshcd_readl(hba, REG_UFS_CFG2) | REG_UFS_CFG2_CGC_EN_ALL,
-               REG_UFS_CFG2);
+       ufshcd_rmwl(hba, REG_UFS_CFG2_CGC_EN_ALL, REG_UFS_CFG2_CGC_EN_ALL,
+                   REG_UFS_CFG2);
 
        /* Ensure that HW clock gating is enabled before next operations */
        mb();
@@ -1689,11 +1688,8 @@ static int ufs_qcom_config_esi(struct ufs_hba *hba)
                platform_msi_domain_free_irqs(hba->dev);
        } else {
                if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 &&
-                   host->hw_ver.step == 0) {
-                       ufshcd_writel(hba,
-                                     ufshcd_readl(hba, REG_UFS_CFG3) | 0x1F000,
-                                     REG_UFS_CFG3);
-               }
+                   host->hw_ver.step == 0)
+                       ufshcd_rmwl(hba, ESI_VEC_MASK, 0x1f00, REG_UFS_CFG3);
                ufshcd_mcq_enable_esi(hba);
        }
 

diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 385480499e710dfaabb0a46446711e5c3016361a..2ce63a1c7f2f1ef321f6c6ae85c8c849721b0ece 100644 (file)
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -102,6 +102,9 @@ enum {
 #define TMRLUT_HW_CGC_EN       BIT(6)
 #define OCSC_HW_CGC_EN         BIT(7)
 
+/* bit definitions for REG_UFS_CFG3 register */
+#define ESI_VEC_MASK           GENMASK(22, 12)
+
 /* bit definitions for REG_UFS_PARAM0 */
 #define MAX_HS_GEAR_MASK       GENMASK(6, 4)
 #define UFS_QCOM_MAX_GEAR(x)   FIELD_GET(MAX_HS_GEAR_MASK, (x))