clk: renesas: r8a779a0: Add CMT clocks

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210311092939.3129-2-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 12607a79314322feef98a0d469a1db6dd8482a25..867c565cb58ff5b50a469e995ded1f65b0d986af 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -233,6 +233,10 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
        DEF_MOD("vspd0",        830,    R8A779A0_CLK_S3D1),
        DEF_MOD("vspd1",        831,    R8A779A0_CLK_S3D1),
        DEF_MOD("rwdt",         907,    R8A779A0_CLK_R),
+       DEF_MOD("cmt0",         910,    R8A779A0_CLK_R),
+       DEF_MOD("cmt1",         911,    R8A779A0_CLK_R),
+       DEF_MOD("cmt2",         912,    R8A779A0_CLK_R),
+       DEF_MOD("cmt3",         913,    R8A779A0_CLK_R),
        DEF_MOD("pfc0",         915,    R8A779A0_CLK_CP),
        DEF_MOD("pfc1",         916,    R8A779A0_CLK_CP),
        DEF_MOD("pfc2",         917,    R8A779A0_CLK_CP),